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Many problems faced in the engineering world are computationally intensive. Filtering using FIR (Finite Impulse Response) filters is an example to that. This thesis discusses the implementation of a fast, reconfigurable, and scalable FIR (Finite Impulse Response) digital filter. Constant coefficient multipliers and a Fast FIFO implementation are also discussed in connection with the FIR filter. This filter is used in two of its structures: the direct-form and the lattice structure. The thesis describes several configurations that can be created with the different components available and reports the testing results of these configurations. / Master of Science

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No / Finite impulse response (FIR) digital filters are extensively used due to their key role in various digital signal processing (DSP) applications. Several attempts have been made to develop hardware realization of FIR filters characterized by implementation complexity, precision and high speed. Field Programmable Gate Array is a reconfigurable realization of FIR filters. Field-programmable gate arrays (FPGAs) are on the verge of revolutionizing digital signal processing. Many front-end digital signal processing (DSP) algorithms, such as FFTs, FIR or IIR filters, are now most often realized by FPGAs. Modern FPGA families provide DSP arithmetic support with fast-carry chains that are used to implement multiply-accumulates (MACs) at high speed, with low overhead and low costs. In this paper, distributed arithmetic (DA) realization of FIR filter as serial and parallel are discussed in terms of hardware cost and resource utilization.

State of the art filter bank structures achieve practically perfect reconstruction with very high computational efficiency. However, the increase in computational requirements due to the need to process increasingly wider band signals is paramount. New filter bank structures that provide extra information about a signal while achieving the same level of required efficiency, and perfect reconstruction properties, need to be developed. In this work a new filter bank structure, the interpolated FIR (IFIR) filter bank is developed. Such a structure combines the concepts of filter banks, and interpolated FIR filters. The filter design procedures for the IFIR filter bank are developed and explained. The resulting structure was compared with the non-maximally-decimated filter bank (NMDFB), achieving the same performance in terms of the number of multiplications required per sample and the overall distortion introduced by the system, when operating with Nyquist prototype filters. In addition, the IFIR filter is tested in both simulated and real communication environments. Performance, in terms of bit-error-rate, was found to not be degraded significantly when using the IFIR filter bank system for transmission and reception of QPSK symbols. / Master of Science

The main issue in this thesis is to minimize the energy consumption per operation for the arithmetic parts of DSP circuits, such as digital filters. More specific, the focus is on single- and multiple-constant multiplications, which are realized using shift-and-add based computations. The possibilities to reduce the complexity, i.e., the chip area, and the energy consumption are investigated. Both serial and parallel arithmetic are considered. The main difference, which is of interest here, is that shift operations in serial arithmetic require flip-flops, while shifts can be hardwired in parallel arithmetic.The possible ways to connect a given number of adders is limited. Thus, for single-constant multiplication, the number of shift-and-add structures is finite. We show that it is possible to save both adders and shifts compared to traditional multipliers. Two algorithms for multiple-constant multiplication using serial arithmetic are proposed. For both algorithms, the total complexity is decreased compared to one of the best-known algorithms designed for parallel arithmetic. Furthermore, the impact of the digit-size, i.e., the number of bits to be processed in parallel, is studied for FIR filters implemented using serial arithmetic. Case studies indicate that the minimum energy consumption per sample is often obtained for a digit-size of around four bits.The energy consumption is proportional to the switching activity, i.e., the average number of transitions between the two logic levels per clock cycle. To achieve low power designs, it is necessary to develop accurate high-level models that can be used to estimate the switching activity. A method for computing the switching activity in bit-serial constant multipliers is proposed.For parallel arithmetic, a detailed complexity model for constant multiplication is introduced. The model counts the required number of full and half adder cells. It is shown that the complexity can be significantly reduced by considering the interconnection between the adders. A main factor for energy consumption in constant multipliers is the adder depth, i.e., the number of cascaded adders. The reason for this is that the switching activity will increase when glitches are propagated to subsequent adders. We propose an algorithm, where all multiplier coefficients are guaranteed to be realized at the theoretically lowest depth possible. Implementation examples show that the energy consumption is significantly reduced using this algorithm compared to solutions with fewer word level adders.For most applications, the input data are correlated since real world signals are processed. A data dependent switching activity model is derived for ripple-carry adders. Furthermore, a switching activity model for the single adder multiplier is proposed. This is a good starting point for accurate modeling of shift-and-add based computations using more adders.Finally, a method to rewrite an arbitrary function as a sum of weighted bit-products is presented. It is shown that for many elementary functions, a majority of the bit-products can be neglected while still maintaining reasonable high accuracy, since the weights are significantly smaller than the allowed error. The function approximation algorithms can be implemented using a low complexity architecture, which can easily be pipelined to an arbitrary degree for increased throughput.

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior / Esta dissertação tem como objetivo aplicar um algoritmo genético (GA) ao projeto de filtros FIR com coeficientes quantizados representados em somas de potências de dois com sinal (SPT). Os filtros FIR apresentam configurações que permitem a obtenção de fase linear, atributo desejado em diversas aplicações que necessitam de atraso de grupo constante. A representação SPT, de fácil implementação em circuitos, foi discutida e uma comparação das representações SPT mínimas e canônicas foi feita, baseada no potencial de redução de operações e na variedade de valores representáveis. O GA é aplicado na otimização dos coeficientes SPTs do filtro, para que este cumpra as suas especificações de projeto. Foram feitas análises sobre o efeito que diversos parâmetros do GA como a intensidade de seleção, tamanho das populações, cruzamento, mutação, entre outros, têm no processo de otimização. Foi proposto um novo cruzamento que produz a recombinação dos coeficientes e que obteve bons resultados. Aplicou-se o algoritmo obtido na produção de filtros dos tipos passa-baixas, passa-altas, passa-faixas e rejeita-faixas.

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior / Esta dissertação tem como objetivo aplicar um algoritmo genético (GA) ao projeto de filtros FIR com coeficientes quantizados representados em somas de potências de dois com sinal (SPT). Os filtros FIR apresentam configurações que permitem a obtenção de fase linear, atributo desejado em diversas aplicações que necessitam de atraso de grupo constante. A representação SPT, de fácil implementação em circuitos, foi discutida e uma comparação das representações SPT mínimas e canônicas foi feita, baseada no potencial de redução de operações e na variedade de valores representáveis. O GA é aplicado na otimização dos coeficientes SPTs do filtro, para que este cumpra as suas especificações de projeto. Foram feitas análises sobre o efeito que diversos parâmetros do GA como a intensidade de seleção, tamanho das populações, cruzamento, mutação, entre outros, têm no processo de otimização. Foi proposto um novo cruzamento que produz a recombinação dos coeficientes e que obteve bons resultados. Aplicou-se o algoritmo obtido na produção de filtros dos tipos passa-baixas, passa-altas, passa-faixas e rejeita-faixas.

In video transmission there is a need to compose a wide-band signal from a numberof narrow-band sub-signals. A flexible solution offers the possibility to place any narrow-band sub-signal anywhere in the wide-band signal, making better use of the frequency space of the wide-band signal. A multi-standard supportive solution will also consider the three standard bandwidths of digital and analog video transmissions, both terrestrial and cable (6; 7 and 8 MHz), in use today. This thesis work will study the efficiency of a flexible aggregation solution, in terms of computational complexity and error vector magnitude (EVM). The solution uses oversampled complex modulated filter banks and inner channelizers, to reduce the total workload on the system. Each sub-signal is channelized through an analysis filter bank and together all channelized sub-signals are aggregated through one synthesis filter bank to form the wide-band composite signal. The EVM between transmitted and received sub-signals are investigated for an increasing number of sub-signals. The solution in this thesis work is performing good for the tested number of up to 100 narrow-band sub-signals. The result indicates that the multi-standard flexible aggregation solution is efficient for an increasing number of transmitted sub-signals.