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This work is a study of a hybrid adaptive controller that blends fixed feedback control and adaptive feedback control techniques. This type of adaptive controller removes the requirement that information about the disturbance is known apriori. Additionally, the control structure is implemented in such a way that as long as the adaptive controller is stable during adaptation, the system consisting of the controller and plant remain stable. The objective is to design and implement an adaptive controller that damps the structural vibrations induced in a multi-modal structure. The adaptive controller utilizes an adaptive infinite impulse response lattice filter for improved damping over the fixed feedback controller alone. An adaptive finite impulse response LMS filter is also implemented for comparison of the ability for both algorithms to reject harmonic, narrow bandwidth and wide bandwidth disturbances. It is demonstrated that the lattice filter algorithm performs slightly better than the LMS filter algorithm in all three disturbance cases. The lattice filter also requires less than half the order of the LMS filter to get the same performance. / Master of Science

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No / Finite impulse response (FIR) digital filters are extensively used due to their key role in various digital signal processing (DSP) applications. Several attempts have been made to develop hardware realization of FIR filters characterized by implementation complexity, precision and high speed. Field Programmable Gate Array is a reconfigurable realization of FIR filters. Field-programmable gate arrays (FPGAs) are on the verge of revolutionizing digital signal processing. Many front-end digital signal processing (DSP) algorithms, such as FFTs, FIR or IIR filters, are now most often realized by FPGAs. Modern FPGA families provide DSP arithmetic support with fast-carry chains that are used to implement multiply-accumulates (MACs) at high speed, with low overhead and low costs. In this paper, distributed arithmetic (DA) realization of FIR filter as serial and parallel are discussed in terms of hardware cost and resource utilization.