This thesis proposes a low-IF receiver architecture suitable for the realization of single-chip receivers. To alleviate the image-rejection requirements of the front-end filters an oversampling complex discrete-time ΔΣ ADC with a signal-transfer function that achieves a significant filtering of interfering signals is proposed. A filtering ADC reduces the complexity of the receiver by minimizing the requirements of analog filters in the IF digitization path. Discrete-time ΔΣ ADCs have precise resonant frequency and clock frequency ratios and, hence, do not require the calibration or tuning that is necessary in the case of continuous-time ΔΣ modulator implementations. This feature makes the proposed discrete- time ΔΣ ADC ideal for multistandard receiver applications.

This thesis proposes a low-IF receiver architecture suitable for the realization of single-chip receivers. To alleviate the image-rejection requirements of the front-end filters an oversampling complex discrete-time ΔΣ ADC with a signal-transfer function that achieves a significant filtering of interfering signals is proposed. A filtering ADC reduces the complexity of the receiver by minimizing the requirements of analog filters in the IF digitization path. Discrete-time ΔΣ ADCs have precise resonant frequency and clock frequency ratios and, hence, do not require the calibration or tuning that is necessary in the case of continuous-time ΔΣ modulator implementations. This feature makes the proposed discrete- time ΔΣ ADC ideal for multistandard receiver applications.

Nowadays, Sigma-Delta analog-to-digital converters have been widely used in the technology of analog-to-digital conversion. It depends on the merits that the approach of Sigma-Delta has. The signal converted by oversampling is precise and well-suited in signal processing systems.This thesis mainly focuses on the principles and simulations of fundamental first-order Sigma-Delta converter, and some brief introductions about other Sigma-Delta converters.The main researches of this thesis are as follows: (1)This thesis shows not only the path about development of technology of different ADCs, but also the features and principles of these ADCs and their structures. (2)The thesis discusses how the technologies of oversampling and noise shaping are used in Sigma-Delta analog-to-digital conversion. (3)Illustrate different orders Sigma-Delta converters in different bits and their advantages and disadvantages, respectively. (4)The simulation is given in Matlab(Simulink). Typical first-order SigmaDelta converter is simulated with additional noise which will impact the input signal when implement. / Sigma-Delta Converter

The focus of this dissertation is the interpolation and approximation of multivariate bandlimited functions via sampled (function) values. The first set of results investigates polynomial interpolation in connection with multivariate bandlimited functions. To this end, the concept of a uniformly invertible Riesz basis is developed (with examples), and is used to construct Lagrangian polynomial interpolants for particular classes of sampled square-summable data. These interpolants are used to derive two asymptotic recovery and approximation formulas. The first recovery formula is theoretically straightforward, with global convergence in the appropriate metrics; however, it becomes computationally complicated in the limit. This complexity is sidestepped in the second recovery formula, at the cost of requiring a more local form of convergence. The second set of results uses oversampling of data to establish a multivariate recovery formula. Under additional restrictions on the sampling sites and the frequency band, this formula demonstrates a certain stability with respect to sampling errors. Computational simplifications of this formula are also given.

Zugl.: Dresden, Techn. Univ., Diss., 2007

This dissertation explores methods of reducing the oversampling ratio (OSR) of both delta-sigma modulators and incremental data converters. The first reduced-OSR architecture is the high-order cascaded delta-sigma modulator. These delta-sigma modulators are shown to reduce the in-band noise sufficiently at OSRs as low as 3 while providing power savings. The second low OSR architecture is the high-order cascaded incremental data converter which possesses signal-to-quantization noise ratio (SQNR) advantages over equivalent delta-sigma modulators at low OSRs. The final architecture is the time-interleaved incremental data converter where two designs are identified as potential methods of increasing the throughput of low OSR incremental data converters. A prototype chip is designed in 0.18um CMOS technology which can operate in three modes by simply changing the resetting clock phases. It can operate as an 8-stage pipeline analog-to-digital (A/D) converter, an 8th-order cascaded delta-sigma modulator, and an 8th-order cascaded incremental data converter with an OSR of 3.

The main purpose of this thesis is to research High-Order Sigma-Delta Analog-to-Digital converter for precision measurement, a PI compensator and a third-order Sigma-Delta modulator has been proposed based on a second-order Sigma-Delta modulator. In accordance with the analysis result of frequency domain and time domain of system, we use third-order model because of better response with auxiliary software to simulate and implement the system, then measure modulator output variance for input variation. This converter circuit demonstrates that it can achieve the requirements of precision and linearity which the measure instrument demands.

This dissertation explores methods of reducing the oversampling ratio (OSR) of both delta-sigma modulators and incremental data converters. The first reduced-OSR architecture is the high-order cascaded delta-sigma modulator. These delta-sigma modulators are shown to reduce the in-band noise sufficiently at OSRs as low as 3 while providing power savings. The second low OSR architecture is the high-order cascaded incremental data converter which possesses signal-to-quantization noise ratio (SQNR) advantages over equivalent delta-sigma modulators at low OSRs. The final architecture is the time-interleaved incremental data converter where two designs are identified as potential methods of increasing the throughput of low OSR incremental data converters. A prototype chip is designed in 0.18um CMOS technology which can operate in three modes by simply changing the resetting clock phases. It can operate as an 8-stage pipeline analog-to-digital (A/D) converter, an 8th-order cascaded delta-sigma modulator, and an 8th-order cascaded incremental data converter with an OSR of 3.

Within machine learning, the problem of class imbalance refers to the scenario in which one or more classes is significantly outnumbered by the others. In the most extreme case, the minority class is not only significantly outnumbered by the majority class, but it also considered to be rare, or absolutely imbalanced. Class imbalance appears in a wide variety of important domains, ranging from oil spill and fraud detection, to text classification and medical diagnosis. Given this, it has been deemed as one of the ten most important research areas in data mining, and for more than a decade now the machine learning community has been coming together in an attempt to unequivocally solve the problem. The fundamental challenge in the induction of a classifier from imbalanced training data is in managing the prediction bias. The current state-of-the-art methods deal with this by readjusting misclassification costs or by applying resampling methods. In cases of absolute imbalance, these methods are insufficient; rather, it has been observed that we need more training examples. The nature of class imbalance, however, dictates that additional examples cannot be acquired, and thus, synthetic oversampling becomes the natural choice. We recognize the importance of selecting algorithms with assumptions and biases that are appropriate for the properties of the target data, and argue that this is of absolute importance when it comes to developing synthetic oversampling methods because a large generative leap must be made from a relatively small training set. In particular, our research into gamma-ray spectral classification has demonstrated the benefits of incorporating prior knowledge of conformance to the manifold assumption into the synthetic oversampling algorithms. We empirically demonstrate the negative impact of the manifold property on the state-of-the-art methods, and propose a framework for manifold-based synthetic oversampling. We algorithmically present the generic form of the framework and demonstrate formalizations of it with PCA and the denoising autoencoder. Through use of the helix and swiss roll datasets, which are standards in the manifold learning community, we visualize and qualitatively analyze the benefits of our proposed framework. Moreover, we unequivocally show the framework to be superior on three real-world gamma-ray spectral datasets and on sixteen benchmark UCI datasets in general. Specifically, our results demonstrate that the framework for manifold-based synthetic oversampling produces higher area under the ROC results than the current state-of-the-art and degrades less on data that conforms to the manifold assumption.

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