We explore the use of machine learning to detect under-rotation in figure skating jumps. Under- rotation in jumps is difficult for the skater to sense but learning to recognize under-rotation is an impor- tant part of learning proper jump technique. To address this difficulty, we present the Under-rotation Monitor, or UR Monitor, a system for detecting under-rotated figure skating jumps in real-time. UR Monitor uses a single inertial measurement unit (IMU) attached to the skater's waist that sends a stream of accelerometer and gyroscope data to a mobile phone via Bluetooth. The mobile phone creates and sends an input vector of each jump to a web-hosted API that returns a response from our trained classifier indicating whether it considered that jump as 'under-rotated', or 'completed rotation'. The classifier is trained and tested on a collection of 444 jumps, of which only 121 are under-rotated. We also present a process for addressing an imbalanced dataset on which the classifier trains. Our classifier achieves an F1-score of only 0.66, suggesting that noise and imbalance in the data set are significant issues.

Cardio-respiratory dysfunction, sepsis and necrotizing enterocolitis are responsible for a large numberof deaths in the neonatal population. Despite ecient monitoring and screening in Intensive CareUnits, diagnosis prior to clinical symptoms remains a dicult task. Based on Heart Rate Monitoring,the state-of-the-art HeRO system indicates the risk for sepsis and has already proven its ability toreduce mortality in the neonatal ICU. Recent studies have shown that a particular respiratory behaviorknown as ABD-events, can be used as a physiomarker for sepsis and is therefore an early warningsign. Detecting ABD-events is currently done by simple thresholding techniques. Based on cardiorespiratorydata and hindsight from previous patients, we aim at improving the early warning systemby applying machine learning algorithms. Data with higher frequency than those used in the HeROsystem and biological samples are still to be collected, but still, using low frequency data, we managedto obtain a specicity (true positive) of 70% and a sensitivity (true negative) of 65% on manuallylabeled events. In this report, the theoretical framework is presented along with the practical issuesencountered during the project. / Varje år dör många nyfödda barn i hjärtproblem, sepsis och nekrotiserande enterokolit. Att ställadiagnos innan kliniska symptom är uppenbara är fortfarande mycket svårt, trots effektiv övervakningoch screening inom intensivvården. Med hjälp av kontinuerlig hjärtövervakning med hjälp HeROsystemetkan kan risken för sepsis beräknas. Förekomsten av särskilda förändringar i barnets andningsmönster (apné, bradykardi och desaturation - ABD) kan användas som en tidig fysiomarkörför sepsis och fungerar därför som en varningssignal. I nyligen presenterade studier har detta visatsminska dödligheten på neontalavdelningar. Dessa ABD-händelser har fram till nu upptäckts genomenkel tröskelnivåbedömning. Baserat på hjärt- och andningsövervakningsdata och kunskap om tidigarepatienter, vill vi förbättra detta system för tidiga varningssignaler genom att använda maskininlärningsalgoritmer. Analys av högfrekvensdata och biomarkörer kvarstår att göra, men ävenbaserat på lågfrekvensdata kunde vi uppnå en specificitet på 70% och en sensitivitet på 65%. Dennarapport sammanfattar den teoretiska bakgrunden till analysmetoden och diskuterar praktiska frågorsom identiferats under arbetets gång.

The automation of most of our activities has led to the continuous production of data that arrive in the form of fast-arriving streams. In a supervised learning setting, instances in these streams are labeled as belonging to a particular class. When the number of classes in the data stream is more than two, such a data stream is referred to as a multi-class data stream. Multi-class imbalanced data stream describes the situation where the instance distribution of the classes is skewed, such that instances of some classes occur more frequently than others. Classes with the frequently occurring instances are referred to as the majority classes, while the classes with instances that occur less frequently are denoted as the minority classes. Classification algorithms, or supervised learning techniques, use historic instances to build models, which are then used to predict the classes of unseen instances. Multi-class imbalanced data stream classification poses a great challenge to classical classification algorithms. This is due to the fact that traditional algorithms are usually biased towards the majority classes, since they have more examples of the majority classes when building the model. These traditional algorithms yield low predictive accuracy rates for the minority instances and need to be augmented, often with some form of sampling, in order to improve their overall performances. In the literature, in both static and streaming environments, most studies focus on the binary class imbalance problem. Furthermore, research in multi-class imbalance in the data stream environment is limited. A number of researchers have proceeded by transforming a multi-class imbalanced setting into multiple binary class problems. However, such a transformation does not allow the stream to be studied in the original form and may introduce bias. The research conducted in this thesis aims to address this research gap by proposing a novel online learning methodology that combines oversampling of the minority classes with cluster-based majority class under-sampling, without decomposing the data stream into multiple binary sets. Rather, sampling involves continuously selecting a balanced number of instances across all classes for model building. Our focus is on improving the rate of correctly predicting instances of the minority classes in multi-class imbalanced data streams, through the introduction of the Synthetic Minority Over-sampling Technique (SMOTE) and Cluster-based Under-sampling - Data Streams (SCUT-DS) methodologies. In this work, we dynamically balance the classes by utilizing a windowing mechanism during the incremental sampling process. Our SCUT-DS algorithms are evaluated using six different types of classification techniques, followed by comparing their results against a state-of-the-art algorithm. Our contributions are tested using both synthetic and real data sets. The experimental results show that the approaches developed in this thesis yield high prediction rates of minority instances as contained in the multiple minority classes within a non-evolving stream.

This thesis is to deal with the saturation problem arisen from the integrator accumulation in the loop of the sigma-delta analog-to-digital converter. Signal passes through the accumulation of several integrators in the high-order sigma-delta analog-to-digital converter, it tends to result in saturation problem in the output of integrator. This phenomenon is prominent especially in implementation. Unable to correctly propagate signal to the next integrator stage, thus, causes the analog-to-digital converter create incorrect result. Accordingly, this thesis proposes a new anti-windup scheme by means of sliding mode control to tackle the saturation problem. We have successfully set up a criterion for the selection of parameters of the sigma-delta analog-to-digital converter to prevent the integrators from saturation. After extensive simulation and experiment, it can significantly improve the ensemble of the sigma-delta analog-to-digital modulator.

This thesis strives to enhance the performance of delta-sigma modulators in two areas: increasing their speed and enabling their operation in a low voltage environment. Parallelism based on time-interleaving can be used to increase the speed of delta-sigma modulators. A novel single-path time-interleaved architecture is derived and analyzed. Finite opamp gain and bandwidth result in a mismatch between the noise transfer functions of the internal quantizers which degrades the performance of the new modulator. Two techniques are presented to mitigate the mismatch problem: a hybrid topology where the first stage uses multiple integrators while the rest of the modulator uses a single path of integrators and a digital calibration method. The input-feedforward technique removes the input-signal component from the internal nodes of delta-sigma modulators. The removal of the signal component reduces the signal swing and distortion requirements for the opamps. These characteristics enable the reliable implementation of delta-sigma modulators in modern CMOS technology. Two implementation issues for modulators with input-feedforward are considered. First, the drawback of the analog adder at the quantizer input is identified and the capacitive input feedforward technique is introduced to eliminate the adder. Second, the double sampled input technique is proposed to remove the critical path generate by the input feedforward path. Novel input-feedforward delta-sigma architecture is proposed. The new digital input feedforward (DIFF) modulator maintains the low swing and low distortion requirements of the input feedforward technique, it eliminates the analog adder at the quantizer input, and it improves the achievable resolution. To demonstrate these advantages, a configurable delta-sigma modulator which can operate as a feedback topology or in DIFF mode is implemented in 0.18μm CMOS technology. Both modulators operate at 20MHz clock with an oversampling ratio of 8. The power consumption in the DIFF mode is 22mW and in feedback mode is 19mW. However, the DIFF mode achieves a peak SNDR of 73.7dB (77.1dB peak SNR) while the feedback mode achieves a peak SNDR of 64.3dB (65.9dB peak SNR). Therefore, the energy required per conversion step for the DIFF architecture (2.2 pJ/step) is less than half of that required by the feedback architecture (5.7 pJ/step).

This thesis strives to enhance the performance of delta-sigma modulators in two areas: increasing their speed and enabling their operation in a low voltage environment. Parallelism based on time-interleaving can be used to increase the speed of delta-sigma modulators. A novel single-path time-interleaved architecture is derived and analyzed. Finite opamp gain and bandwidth result in a mismatch between the noise transfer functions of the internal quantizers which degrades the performance of the new modulator. Two techniques are presented to mitigate the mismatch problem: a hybrid topology where the first stage uses multiple integrators while the rest of the modulator uses a single path of integrators and a digital calibration method. The input-feedforward technique removes the input-signal component from the internal nodes of delta-sigma modulators. The removal of the signal component reduces the signal swing and distortion requirements for the opamps. These characteristics enable the reliable implementation of delta-sigma modulators in modern CMOS technology. Two implementation issues for modulators with input-feedforward are considered. First, the drawback of the analog adder at the quantizer input is identified and the capacitive input feedforward technique is introduced to eliminate the adder. Second, the double sampled input technique is proposed to remove the critical path generate by the input feedforward path. Novel input-feedforward delta-sigma architecture is proposed. The new digital input feedforward (DIFF) modulator maintains the low swing and low distortion requirements of the input feedforward technique, it eliminates the analog adder at the quantizer input, and it improves the achievable resolution. To demonstrate these advantages, a configurable delta-sigma modulator which can operate as a feedback topology or in DIFF mode is implemented in 0.18μm CMOS technology. Both modulators operate at 20MHz clock with an oversampling ratio of 8. The power consumption in the DIFF mode is 22mW and in feedback mode is 19mW. However, the DIFF mode achieves a peak SNDR of 73.7dB (77.1dB peak SNR) while the feedback mode achieves a peak SNDR of 64.3dB (65.9dB peak SNR). Therefore, the energy required per conversion step for the DIFF architecture (2.2 pJ/step) is less than half of that required by the feedback architecture (5.7 pJ/step).

The filter complexity in the multi-stage decimation system of a Δ-Σ ADC increases progressively as one moves to higher stages of decimation due to the fact that the input word length of the higher stages also increases progressively. The main motivation for this thesis comes from the idea of investigating a way, to reduce the input word length in the later filter stages of the decimation system which could reduce the filter complexity. To achieve this, we use a noise-shaping loop between the first and later stages so that the input word length for the later stages remains smaller than in the case where we do not use the noise-shaping loop. However, the performance (SNR/ Noise-level) level should remain the same in both cases. This thesis aims at analyzing the implications of using a noise-shaping loop in between the decimation stages of a Δ-Σ ADC and also finding the appropriate decimation filter types that could be used in such a decimation system. This thesis also tries to compare the complexity introduced by using the noise-shaping loop with the reduction achieved in the later decimation stages in terms of the input word length. Filter required in the system will also be optimized using minimax optimization technique.

The main goal of this thesis is to study the saturation problem arisen from the integrator in a sigma- delta analog- to- digital modulator , especially when the order of the circuit is higher than two .Signal passes through each stage of integrators yield saturation problem. This situation will miss some part of messages .Unable to deliver datas accurately to next stage of the integrator , the output digital signals will be incorrect and can't be recovered to original analog signals . Hence, this thesis proposes an anti-wind-up method by taking sliding mode control theory to avoid integrator saturation. After that, we are going to design and implement two third order sigma-delta modulators based on this method. Simulation and experiment results show the validity of the method and the significant improvement of avoiding saturation problem, and guarantee the designed circuits can translate signals to terminal accurately .

Το αντικείμενο της εργασίας είναι ο υπολογισμός του καρδιακού και αναπνευστικού παλμού με επεξεργασία του σήματος που λαμβάνεται με χρήση πιεζοηλεκτρικού αισθητήρα. Ο αισθητήρας είναι τοποθετημένος στον λαιμό και ανιχνεύει ένα σήμα που περιλαμβάνει τόσο τον καρδιακό, όσο και τον αναπνευστικό ρυθμό. Η δειγματοληψία και μετατροπή του σήματος σε ψηφιακό γίνεται με χρήση του microcontroller MSP430F149 ο οποίος προγραμματίζεται κατάλληλα για το σκοπό αυτό. Το ψηφιακό αυτό σήμα επεξεργάζεται με κατωδιαβατό φίλτρο πεπερασμένης κρουστικής απόκρισης προκειμένου να αποκοπούν οι υψηλές συχνότητες και υπολογίζεται η ενέργεια του προκύπτοντος σήματος. Εν συνεχεία με χρήση του FFT, και κατάλληλων φίλτρων γίνεται ο διαχωρισμός του σήματος σε αναπνοής και καρδιακού ρυθμού. / -

Κατά τις δύο τελευταίες δεκαετίες έχουν αναπτυχθεί ενσωματωμένα συστήματα λήψης σημάτων φυσιολογίας που είναι ελαφριά, μικρά και ικανά να καταγράφουν σύνθετα σήματα για περισσότερες από 48 ώρες. Αυτά τα συστήματα χρησιμοποιούνται στις μελέτες ηλεκτροκαρδιογραφίας (ECG) για να εντοπίζουν σποραδικές καρδιακές αρρυθμίες ή ανωμαλίες στην καρδιακή λειτουργία, που συχνά σχετίζονται με τις εντάσεις της καθημερινότητας. Σήμερα τα καρδιακά σήματα καταγράφονται σε κάρτες μνήμης και μπορούν εύκολα να μεταφερθούν για ανάλυση και επεξεργασία. Με την εξέλιξη της τεχνολογίας, οι κατασκευαστές ιατρικού εξοπλισμού περιόρισαν δραστικά το μέγεθος και την κατανάλωση ενέργειας των συσκευών καταγραφής ΗΚΓ, έτσι ώστε αυτές να αποκτήσουν αυτονομία. Στην εργασία αυτή θα παρουσιαστεί ένα ενσωματωμένο σύστημα καταγραφής, αποθήκευσης και επεξεργασίας ηλεκτροκαρδιογραφικών σημάτων, ώστε να επιτυγχάνεται η παρακολούθηση των ζωτικών ενδείξεων ασθενών με αρρυθμίες και καρδιακή ανεπάρκεια Η εργασία αυτή χωρίζεται ουσιαστικά σε έξι τμήματα. Το πρώτο τμήμα ασχολείται με την φυσιολογία της καρδιάς, η οποία αποτελεί την πηγή του ηλεκτροκαρδιογραφήματος, καθώς και με την δομή ενός ηλεκτροκαρ-διογράφου και τους τρόπους με τους οποίους μπορούμε να το πάρουμε από τα διάφορα σημεία του ανθρώπινου σώματος. Τα επόμενα δύο τμήματα που ακολουθούν αφορούν την χρήση και τις δυνατότητες των ενσωματωμένων συστημάτων και μικροελεγκτών με έμφαση στην παρουσίαση του μικροελεγκτή (ADuC 7026) και των περιφερειακών του που θα χρησιμοποιηθούν για την υλοποίηση. Παράλληλα αναλύεται το περιβάλλον μVision της Keil το οποίο παρέχει τη δυνατότητα εξομοίωσης του μικροελεγκτή μας έχοντας στη διαθεσή μας μηδενικό υλικό. Το τρίτο τμήμα συνοψίζει κάποιες βασικές λειτουργίες προγραμματισμού και δυνατότητες που παρουσιάζει ο ADuC 7026 της Analog Devices. Το τέταρτο τμήμα ασχολείται με μεθόδους ψηφιακής επεξεργασίας σημάτων χαμηλής συχνότητας για την απομάκρυνση του θορύβου και την αύξηση της ευκρίνειας των αποτελεσμάτων. Τα δύο τελευταία τμήματα περιέχουν αναλυτικά τις μεθόδους επεξεργασίας που χρησιμοποιήθηκαν για τον προγραμματισμό του μικροελεγκτή και παραθέτονται τα αντίστοιχα αποτελέσματα. Για την υλοποίηση χρησιμοποιήθηκαν αρχικά προσεγγιστικά σήματα για τη μοντελοποίηση των πραγματικών σημάτων που προκύπτουν από την καρδιοαναπνευστική λειτουργία . Γίνεται τέλος με τη βοήθεια του matlab πλήρης αναδημιουργία του καρδιακού παλμού και εξάγονται τα κατάλληλα συμπεράσματα. Ο προγραμματισμός του μικροελεγκτή έγινε σε γλώσσα προγραμματισμού C. / During the two last decades there have been developed embedded systems , for the receive of physiology signals. that are small light and able to record composite signals for more than 48 hours. These systems are used at research on electrocardiography(ECG) for the locating of sporadic cardiac arrhythmias,or abnormal heart function, often associated with the stresses of everyday life. Nowadays, cardiac signals recorded on memory cards and can easily be transferred for analysis and processing. Through the technological evolution, medical equipment manufacturers have reduced drastically the size and power consumption of the ECG recorders, so that they can be autonomous. At this thesis, an embedded system for recording, saving and processing ECG signals is presented. The main purpose is to achieve the monitoring of vital signs of patients with arrhythmias and heart failure. The thesis is divided into six sections. The first part deals with the physiology of the heart, which is the source of the electrocardiogram and the structure of an electrocardiograph and how we can get it from different parts of the human body. The next two sections below cover the use and potential of embedded systems and microcontrollers with an emphasis on presentation of the microcontroller (ADuC 7026) and its peripherals that will be used for implementation. At the same time explaining the μVision the Keil environment which enables us to emulate the microcontroller having at our disposal zero hardware. The third section summarizes some basic functions and programming possibilities presented by ADuC 7026 of Analog Devices. The fourth part deals with methods of digital signal processing of low frequency to remove noise and increase clarity of results. The last two sections contain detailed the processes used for programming the microcontroller and presents the corresponding results. During the implementation, initially approximated signals were used for modeling of real signals arising from cardiopulmonary function. Finally, using matlab we achieve a full reconstruction of the heart beat and drew the appropriate conclusions. The programming of the microcontroller has been done in C