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Digital implementation of a mismatch-shaping successive-approximation ADCCoe, Matthew T. 15 October 2001 (has links)
Utilizing a two-capacitor topology, the digital implementation of an audio-band
successive-approximation analog-to-digital converter (ADC) is explored in the
context of mismatch-shaping where the mismatch estimates are accurate to the first
order. A second-order ����� loop was found to be effective in system simulations
given a 0.1% capacitor mismatch. Spectral analysis of the ADC shows dramatic
improvements in total harmonic distortion as well as 87 dB SNDR (signal to noise
and distortion ratio) for an oversampling ratio of 10. / Graduation date: 2002
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20-stage pipelined ADC with radix-based calibrationYun, Chong Kyu 07 November 2002 (has links)
A radix-based calibration technique was previously proposed with a two-stage
algorithmic analog-to-digital converter (ADC). The objective of this work is to verify
the capability of radix-based calibration for a true multi-stage ADC. In order to prove
the idea, a single bit-per-stage, 20-stage pipelined ADC is designed in a 0.35-��m
CMOS technology. The system is fully differential and requires two non-overlapping
clock phases to operate. The implementation of the calibration technique in the
pipelined ADC is investigated. Simulation results show that 109dB of SNDR,
112dB of THD, and 116dB of SFDR can be achieved, which indicates the overall
accuracy of the ADC is 18 bits. / Graduation date: 2003
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Current-mode flash analog-to-digital converterMaleki, Mohammad 30 November 1992 (has links)
This thesis describes the development of a flash analog-to-digital converter based on
current-mode technique. The advantages of current -mode technique are higher speed,
smaller chip area, and simple division of reference current based on current mirror. A
current-mode comparator is designed consisting of a cascode current mirror and a
current sense amplifier used as a latch. The new method allows effective and simple
high-speed A/D conversion where the input is a current signal and the output of the
latch is a digital voltage signal. A four-bit flash analog-to-digital converter, using
current sense amplifier comparator is designed and simulated in 1-micron CMOS
technology. Simulation results show that for ADC with resolution below six-bit, this
technique offers a comparable accuracy with the existing voltage-mode methods at
much higher speed. / Graduation date: 1993
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A subranging analog to digital converter using four bit pipeplinePress, Stephen E. 26 January 1993 (has links)
This thesis presents the design of a 10 bit Analog to
Digital Converter which consists of a 6 bit flash followed
by a 4 bit pipeline architecture. The total system is
described and the 4 bit pipeline is implemented on a bipolar
process.
The objective of this research is to provide an
alternative approach to high speed ADC designs and to
implement a pipeline ADC which samples at greater speeds
than those achieved with presently existing CMOS pipeline
designs.
This paper presents the complete architecture, the cell
design and simulated performance for each block in the
pipeline, and the measured results for the four bit pipeline
implementation. / Graduation date: 1993
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A Low-Power Low-Cost 256MHzS/s 6-bit Analog to Digital Converter Using Selective Reference VoltageShieh, Chung-Hsiao 05 July 2005 (has links)
In this paper, we present a low-power low-cost 6-bits, ADC using selective reference voltage technique. Using selective reference voltage technique, the different bit uses different comparator can be achieved. Meanwhile, the outputs from comparators are a binary code which can be used for generating logic condition thereby controlling the switches. Because the conventional n bits flash ADC requires 2n - 1 comparators and its power, area and input capacitance are all proportional to 2n - 1. Whereas, the proposed n bits ADC needs only n comparators which can save more power and area, and its input capacitance are proportional to n only, and keep high speed.
Our proposed ADC is design by TSMC 1P6M 0.18£gm process with 6-bits resolution, 1.8V power supply. The signal input range 0.5V~1.1V, sampling rate 256MS/s, DNL +0.46LSB~ -0.49LSB, INL +0.85LSB~ -0.05LSB. In addition, the FOM of the ADC is only 0.26 pJ/Conv and the power consumption is only 4.2mW.It is good for a low-power and low cost customer electronic application.
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A 16 Bit 500KSps low power successive approximation analog to digital converterYang, Kun. January 2009 (has links) (PDF)
Thesis (M.S. in electrical engineering)--Washington State University, December 2009. / Title from PDF title page (viewed on Feb. 9, 2010). "School of Electrical Engineering and Computer Science." Includes bibliographical references (p. 42-43).
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Multiband analog-to-digital conversion /Saucier, Scott, January 2002 (has links)
Thesis (M.S.) in Electrical Engineering--University of Maine, 2002. / Includes vita. Bibliography: leaves 94-95.
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Charge-coupled devices for analog-to-digital conversionMichelson, Robert Carroll 12 1900 (has links)
No description available.
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An incremental analog-to-digital converterWilliamson, Frank Robert 08 1900 (has links)
No description available.
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Aspects of designing a high speed analog to digital converter /Hsu, M. S. January 1992 (has links) (PDF)
Thesis (M. Eng. Sc.)--University of Adelaide, Dept. of Electrical and Electronic Engineering, 1994? / Includes bibliographical references (leaves 212-223).
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