Utilizing a two-capacitor topology, the digital implementation of an audio-band successive-approximation analog-to-digital converter (ADC) is explored in the context of mismatch-shaping where the mismatch estimates are accurate to the first order. A second-order ����� loop was found to be effective in system simulations given a 0.1% capacitor mismatch. Spectral analysis of the ADC shows dramatic improvements in total harmonic distortion as well as 87 dB SNDR (signal to noise and distortion ratio) for an oversampling ratio of 10. / Graduation date: 2002

A radix-based calibration technique was previously proposed with a two-stage algorithmic analog-to-digital converter (ADC). The objective of this work is to verify the capability of radix-based calibration for a true multi-stage ADC. In order to prove the idea, a single bit-per-stage, 20-stage pipelined ADC is designed in a 0.35-��m CMOS technology. The system is fully differential and requires two non-overlapping clock phases to operate. The implementation of the calibration technique in the pipelined ADC is investigated. Simulation results show that 109dB of SNDR, 112dB of THD, and 116dB of SFDR can be achieved, which indicates the overall accuracy of the ADC is 18 bits. / Graduation date: 2003

This thesis describes the development of a flash analog-to-digital converter based on current-mode technique. The advantages of current -mode technique are higher speed, smaller chip area, and simple division of reference current based on current mirror. A current-mode comparator is designed consisting of a cascode current mirror and a current sense amplifier used as a latch. The new method allows effective and simple high-speed A/D conversion where the input is a current signal and the output of the latch is a digital voltage signal. A four-bit flash analog-to-digital converter, using current sense amplifier comparator is designed and simulated in 1-micron CMOS technology. Simulation results show that for ADC with resolution below six-bit, this technique offers a comparable accuracy with the existing voltage-mode methods at much higher speed. / Graduation date: 1993

This thesis presents the design of a 10 bit Analog to Digital Converter which consists of a 6 bit flash followed by a 4 bit pipeline architecture. The total system is described and the 4 bit pipeline is implemented on a bipolar process. The objective of this research is to provide an alternative approach to high speed ADC designs and to implement a pipeline ADC which samples at greater speeds than those achieved with presently existing CMOS pipeline designs. This paper presents the complete architecture, the cell design and simulated performance for each block in the pipeline, and the measured results for the four bit pipeline implementation. / Graduation date: 1993

Thesis (M.S. in electrical engineering)--Washington State University, December 2009. / Title from PDF title page (viewed on Feb. 9, 2010). "School of Electrical Engineering and Computer Science." Includes bibliographical references (p. 42-43).

Thesis (M.S.) in Electrical Engineering--University of Maine, 2002. / Includes vita. Bibliography: leaves 94-95.

No description available.

No description available.

Thesis (M. Eng. Sc.)--University of Adelaide, Dept. of Electrical and Electronic Engineering, 1994? / Includes bibliographical references (leaves 212-223).

Thesis (Ph.D.) - University of Glasgow, 2008. / Ph.D. thesis submitted to the Department of Electronics and Electrical Engineering, Faculty of Engineering, University of Glasgow, 2008. Includes bibliographical references. Print version also available.