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Call number: LD2668 .T4 1984 S63 / Master of Science

published_or_final_version / Electrical and Electronic Engineering / Master / Master of Philosophy

在大量的實驗和應用系統中，精確的時間間隔測量是非常重要的。時間-數字轉換器 (TDC) 是一種將兩個輸入脈衝之間的到達時間差轉換成數字編碼的系統。TDC廣泛應用於高能粒子探測器、激光測距儀、數字存儲示波器與及全數字鎖相環中。由於一個TDC的性能對整個系統的性能有極大影響，它吸引了大量的相關研究。 / 現在，基於設計較為簡單，以及分辨率可自然隨工藝而進步，以時延元件方式實現的TDC大大多於以密集模擬電路方式實現的TDC。不過，設計基於時延線的高分辨率TDC時也面對一定挑戰。首先，當TDC的動態範圍增加，時延單元(基本時間測量單元)的數目將呈指數增長，這大大增加了功耗。更糟的是，當時延單元增加時，每個單元中電路噪聲和不匹配引起的線性誤差會沿時延線積累，使TDC的分辨率變差和線性誤差變大。此外，因為制程限制了時延單元最低時延，所以TDC可達到的最低步長亦受此限制。雖然先前有其他研究提出一系列方法超越制程限制以提高時間分辨率，但是它們也有一些不足，例如時延單元數量需要大大增加。 / 在這篇論文中，我們專注於設計高分辨率的TDC。首先，為了減小在TDC中時延元件的數目，我們提出一個基於威尼爾-並行時延線 (Vernier Parallel Delay Line) 的兩段TDC。我們提出通過串聯兩組分辨率略有差異的平行時延線，以致整個TDC的分辨率比當中任何一組的更好。在這樣的配置下，因為首級時延線同時成為第一級TDC，所以時延元件的數目，相比單級TDC所需的大大降低。此外，VPDL令致兩組時延線的延遲步長接近，從而降低時延單元的時延要求，而同一個時延元件設計也可用在兩級的TDC中，以簡化電路設計。 / 第二，為了改善VPDL TDC中的線性誤差和偏移問題，我們提出了一個校準方案。這個校準方案是通過改變時延單元成為可調步長單元，以形成一個數字反饋迴路以調整時延/測量TDC中每步的步長，然後根據該信息調整作校準。這個方案中，時延單元既用作調整時延，也作為校準的參考，所以沒有需要從外部輸入/內部產生準確的定時信號。這簡化了校準過程。 / 第三，我們提出了一個建模方法，以提供一個加快系統設計和功能驗證的方法。這個建模方法把每個時鐘週期輸入的時間差轉換成實數，使在直接建模方法中存在的精度和仿真步長間權衡問題、建模問題和校準邏輯的瞬態仿真問題得以緩解。 / 最後，我們以UMC 0.13μm CMOS工藝製造了一個6位元的VPDL TDC原型。實驗結果證明這原型實現了5ps的分辨率， 0.6LSB的DNL和0.4LSB的單次測量精度。 / Precise time interval measurement is very important in many experimental and applied systems. Time-to-digital converters (TDC) are one type of such measurement systems, which convert the arrival time difference between two input pulses into digital codes. TDCs find various applications in high energy particle detectors, laser range finders, digital storage oscilloscopes, also in all-digital phase lock loops. Since the performance of a TDC greatly affects the performance of the overall system, it attracts a great deal of research efforts. / TDCs based on delay elements are currently dominant compared to other analog-circuit-intensive implementations, because of their design simplicity and that their resolution is inherently enhanced by technology advancement. However, there are challenges on designing high-resolution delay-line-based TDCs. First, when the full scale of the TDC is increased, the number of delay cells (basic time measurement units) have to be increased exponentially, which greatly increases the power consumption. Even worse, when the number of delay cells increases, circuit noises and mismatch-induced nonlinearity from each cell accumulate along the chain and worsen the resolution and linearity of the TDC. Besides, the achievable finest resolution (i.e., the least significant bit, LSB) of the delay-line-based TDCs is limited by the minimum delay of the delay cells, which is process-dependent. Although a number of methods are proposed previously to improve the time resolution beyond the process restriction, there are shortcomings on those architectures, for example, the increase of delay elements needed for generating refined time reference. / In this thesis, we focus on the design of high resolution TDCs. First, to decrease the number of delay elements in the TDC, a two-stage Vernier Parallel Delay Line (VPDL) based TDC is proposed. By cascading two sets of parallel delay lines with slightly difference in resolution, the overall resolution of the TDC is much finer than that of the two sets. By using the first stage delay line as the time reference of the coarse TDC, the number of delay elements is greatly reduced when compared to single stage ones. Besides that, the VPDL makes the delay step sizes similar between stages utilizing Vernier principle, which relaxes the step size requirement of the delay elements, also facilitating design re-use of delay cells among two stages. / Second, to improve the linearity and offset problems in the proposed TDC architecture, a foreground calibration scheme is proposed. By making the delay cells discretely-tunable with equal step, a digital feedback loop can be formed to tune the delay/ measure the step size of each step, then tune the delay of each cell according to the information. The proposed scheme uses the discretely-tunable delay steps to tune the delay, also as the reference of calibration, so no accurate timing signal is needed from internal/external of the TDC. This simplifies the calibration process. / Third, a behavioral modeling approach is proposed to provide a quick way for system design and functional verification. The proposed modeling approach transforms the input time difference at each clock cycle into amplitude, so that the tradeoff between accuracy and simulation step size, problems on modeling and transient simulation of calibration logic that exist in direct modeling approach are alleviated. / To prove the proposed techniques, a 6-bit prototype TDC is fabricated in a 0.13μm CMOS technology, achieving a LSB of 5ps, DNL of 0.6LSB and single-shot precision of 0.4LSB in measurement. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Ko, Chi Tung. / Thesis (Ph.D.)--Chinese University of Hong Kong, 2013. / Includes bibliographical references. / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstracts in also in Chinese. / Abstract --- p.i / 摘要 --- p.iv / Acknowledgements --- p.vi / Table of Contents --- p.viii / List of Figures --- p.xii / List of Tables --- p.xvii / Chapter Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- What is TDC and Applications of TDCs --- p.1 / Chapter 1.2 --- Objectives of This Research --- p.4 / Chapter 1.3 --- Original Contributions --- p.4 / Chapter 1.4 --- Organization of Thesis --- p.5 / REFERENCES --- p.6 / Chapter Chapter 2 --- Fundamentals of TDCs --- p.8 / Chapter 2.1 --- Performance Measures --- p.8 / Chapter 2.1.1 --- Step Size --- p.8 / Chapter 2.1.2 --- Single-shot Precision --- p.9 / Chapter 2.1.3 --- Dynamic Range (DR) --- p.9 / Chapter 2.1.4 --- Linearity --- p.9 / Chapter 2.1.4.1 --- Differential Non-linearity (DNL) --- p.9 / Chapter 2.1.4.2 --- Integral Non-linearity (INL) --- p.10 / Chapter 2.2 --- Types of TDCs --- p.11 / Chapter 2.2.1 --- Analog Method --- p.12 / Chapter 2.2.1.1 --- Time-to-amplitude Converter and ADC [2-6], [2-8] --- p.12 / Chapter 2.2.2 --- Digital Methods --- p.13 / Chapter 2.2.2.1 --- Counters --- p.13 / Chapter 2.2.2.2 --- Delay Line --- p.15 / Chapter 2.2.2.3 --- Vernier Delay Line --- p.16 / Chapter 2.2.2.4 --- Parallel Delay Line --- p.18 / Chapter 2.2.2.5 --- Gated-ring Oscillator (GRO) --- p.20 / Chapter 2.2.2.6 --- Time Amplifier --- p.21 / Chapter 2.3 --- TDC Architecture: Multi-stage vs Single stage TDC --- p.23 / Chapter 2.4 --- Summary --- p.25 / REFERENCES --- p.26 / Chapter Chapter 3 --- Two-stage Vernier Parallel Delay Line (VPDL) TDC with DNL and Offset Calibration --- p.28 / Chapter 3.1 --- Proposed TDC Architecture - Vernier Parallel Delay Line (VPDL) --- p.28 / Chapter 3.2 --- Advantages and Limitation of VPDL TDC --- p.32 / Chapter 3.3 --- Latch buffer --- p.33 / Chapter 3.4 --- Offset and DNL Problems of VPDL TDC --- p.34 / Chapter 3.4.1 --- Latch Buffer Offset --- p.35 / Chapter 3.4.2 --- Latch Offset --- p.37 / Chapter 3.4.3 --- Delay Element Offset --- p.39 / Chapter 3.5 --- Proposed Offset and DNL Calibration Scheme --- p.42 / Chapter 3.5.1 --- Offset Calibration --- p.42 / Chapter 3.5.2 --- DNL Calibration --- p.45 / Chapter 3.5.3 --- Digital Error Correction --- p.51 / REFERENCES --- p.56 / Chapter Chapter 4 --- Behavioral Modeling and System Design of TDC --- p.57 / Chapter 4.1 --- TDC Behavioral Modeling --- p.57 / Chapter 4.1.1 --- Direct Modeling Approach --- p.57 / Chapter 4.1.1.1 --- Modeling of Circuit Blocks --- p.58 / Chapter 4.1.1.2 --- Limitations of Direct Modeling Approach --- p.60 / Chapter 4.1.2 --- Proposed Modeling Approach --- p.61 / Chapter 4.1.2.1 --- Transformation of Time Delay --- p.62 / Chapter 4.1.2.2 --- Modeling of Different Circuit Blocks --- p.64 / Chapter 4.1.2.2.1 --- Delay Cells --- p.64 / Chapter 4.1.2.2.2 --- Sampling Latches --- p.66 / Chapter 4.1.2.2.3 --- DTC --- p.68 / Chapter 4.1.2.2.4 --- Calibration Logic --- p.69 / Chapter 4.1.2.3 --- Limitation on the Proposed Approach --- p.72 / Chapter 4.2 --- System Overview of TDC --- p.73 / Chapter 4.2.1 --- Circuit Block Specifications --- p.77 / Chapter 4.2.1.1 --- Calibration Step Sizes --- p.77 / Chapter 4.2.1.2 --- Effect of Latch Offset Mismatch --- p.80 / Chapter 4.2.1.3 --- Effect of Calibration Step Size Mismatches --- p.86 / Chapter 4.3 --- Summary --- p.89 / REFERENCES --- p.89 / Chapter Chapter 5 --- Circuit Implementation and Simulation Results of the TDC --- p.91 / Chapter 5.1.1 --- Sampling Latch --- p.91 / Chapter 5.1.2 --- Delay Cells --- p.95 / Chapter 5.1.2.1 --- Comparison of Jitter between Differential Pair and Single-ended Delay Line --- p.95 / Chapter 5.1.2.2 --- Circuit Design --- p.103 / Chapter 5.1.3 --- Residue Routing Switch --- p.107 / Chapter 5.2 --- Transistor-level Simulation Results --- p.109 / Chapter 5.3 --- Summary --- p.114 / REFERENCES --- p.114 / Chapter Chapter 6 --- Physical Design and Experimental Results of the TDC --- p.117 / Chapter 6.1 --- Physical Design of TDC --- p.117 / Chapter 6.1.1 --- Floor Planning --- p.117 / Chapter 6.1.2 --- Delay Cell --- p.120 / Chapter 6.2 --- Experimental Results --- p.123 / Chapter 6.2.1 --- Measurement Setup --- p.123 / Chapter 6.2.2 --- Calibration Procedure --- p.126 / Chapter 6.2.3 --- Measurement Procedure --- p.130 / Chapter 6.2.4 --- Measurement Results --- p.130 / Chapter 6.2.4.1 --- TDC1 Measurement --- p.131 / Chapter 6.2.4.2 --- Overall TDC Measurement --- p.133 / Chapter 6.3 --- Summary --- p.141 / REFERENCES --- p.144 / Chapter Chapter 7 --- Conclusions and Future Works --- p.146 / Chapter 7.1 --- Conclusions --- p.146 / Chapter 7.2 --- Future Works --- p.147

Shen Jun-Hua. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2004. / Includes bibliographical references (leaves 151-154). / Abstracts in English and Chinese. / Abstract --- p.ii / 摘要 --- p.iv / Acknowledgments --- p.vi / Table of Contents --- p.vii / List of Figures --- p.ix / List of Tables --- p.xii / Chapter Chapter 1 --- Introduction --- p.1 / Chapter 1.1. --- Overview --- p.1 / Chapter 1.2. --- Motivation and Objectives --- p.5 / Chapter 1.3. --- Original Contributions of This Work --- p.6 / Chapter 1.4. --- Organization of the Thesis --- p.7 / Chapter Chapter 2 --- Sigma-delta Modulation and IF A/D Conversion --- p.8 / Chapter 2.1. --- Introduction --- p.8 / Chapter 2.2. --- Fundamentals of Sigma-delta Modulation --- p.9 / Chapter 2.2.1. --- Feedback Controlled System --- p.9 / Chapter 2.2.2. --- Quantization Noise --- p.11 / Chapter 2.2.3. --- Oversampling and Noise-shaping --- p.11 / Chapter 2.2.4. --- Stability --- p.15 / Chapter 2.2.5. --- Noise Sources --- p.17 / Chapter 2.2.6. --- Baseband Sigma-delta Modulation --- p.28 / Chapter 2.2.7. --- Bandpass Sigma-delta Modulation --- p.28 / Chapter 2.3. --- Discrete-time Sigma-delta Modulation --- p.29 / Chapter 2.4. --- Continuous-time Sigma-delta Modulation --- p.29 / Chapter 2.5. --- IF-input Complex Analog to Digital Converter --- p.31 / Chapter 2.6. --- Image Rejection --- p.32 / Chapter 2.7. --- Integrated Mixer --- p.36 / Chapter Chapter 3 --- High Level Modeling and Simulation --- p.39 / Chapter 3.1. --- Introduction --- p.39 / Chapter 3.2. --- System Level Sigma-delta Modulator Design --- p.40 / Chapter 3.3. --- Continuous-time NTF Generation --- p.46 / Chapter 3.4. --- Discrete-time Sigma-delta Modulator Modeling --- p.50 / Chapter 3.5. --- Continuous-time Sigma-delta Modulator Modeling --- p.52 / Chapter 3.6. --- Modeling of Nonidealities --- p.53 / Chapter 3.7. --- High Level Simulation Results --- p.58 / Chapter Chapter 4 --- Transistor Level Implementation of the Complex Modulator and Layout --- p.65 / Chapter 4.1. --- Introduction --- p.65 / Chapter 4.2. --- IF Input Complex Modulator --- p.65 / Chapter 4.3. --- High IR IF Input Complex Modulator Design --- p.67 / Chapter 4.4. --- System Design --- p.73 / Chapter 4.5. --- Building Blocks Design --- p.77 / Chapter 4.5.1. --- Transconductor Design --- p.77 / Chapter 4.5.2. --- RC Integrator Design --- p.87 / Chapter 4.5.3. --- Gm-C Integrator Design --- p.90 / Chapter 4.5.4. --- Voltage to Current Converter --- p.95 / Chapter 4.5.5. --- Current Comparator Design --- p.96 / Chapter 4.5.6. --- Dynamic Element Matching Design --- p.98 / Chapter 4.5.7. --- Mixer Design --- p.100 / Chapter 4.5.8. --- Clock Generator --- p.103 / Chapter 4.6. --- Transistor Level Simulation of the Design --- p.106 / Chapter 4.7. --- Layout of the Mixed Signal Design --- p.109 / Chapter 4.7.1. --- Layout Overview --- p.109 / Chapter 4.7.2. --- Capacitor layout --- p.110 / Chapter 4.7.3. --- Resistor Layout --- p.113 / Chapter 4.7.4. --- Power and Ground Routing --- p.114 / Chapter 4.7.5. --- OTA Layout --- p.115 / Chapter 4.7.6. --- Chip Layout --- p.117 / Chapter 4.8. --- PostLayout Simulation --- p.120 / Chapter 5. --- Chapter 5 Measurement Results and Improvement --- p.122 / Chapter 5.1. --- Introduction --- p.122 / Chapter 5.2. --- PCB Design --- p.123 / Chapter 5.3. --- Test Setup --- p.125 / Chapter 5.4. --- Measurement of SNR and IRR --- p.128 / Chapter 5.5. --- Discussion of the Chip Performance --- p.131 / Chapter 5.6. --- Design of Robust Sigma Delta Modulator --- p.139 / Chapter Chapter 6 --- Conclusion --- p.148 / Chapter 6.1. --- Conclusion --- p.148 / Chapter 6.2. --- Future Work --- p.150 / Bibliography --- p.151 / Appendix A Schematics of Building Blocks --- p.155 / Author's Publications --- p.157

Zhao, Yinsheng. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2011. / Includes bibliographical references (leaves 90-93). / Abstracts in English and Chinese. / ABSTRACT --- p.I / 摘要 --- p.II / CONTENTS --- p.III / LIST OF FIGURES --- p.V / LIST OF TABLES --- p.VII / ACKNOWLEDGEMENT --- p.VIII / Chapter CHAPTER 1 --- INTRODUCTION --- p.1 / Chapter 1.1 --- MOTIVATION --- p.1 / Chapter 1.2 --- ORGANIZATION OF THE THESIS --- p.5 / Chapter CHAPTER 2 --- BASIC THEOREMS OF DELTA SIGMA ADC --- p.6 / Chapter 2.1 --- INTRODUCTION TO SAMPLING TECHNIQUE --- p.6 / Chapter 2.2 --- DELTA-SIGMA ORDER & NOISE-SHAPING ORDER --- p.8 / Chapter 2.2.1 --- FIRST ORDER CLELTA-SIGMA MODULATOR --- p.8 / Chapter 2.2.2 --- HIGH ORDER DELTA-SIGMA MODULATOR --- p.11 / Chapter 2.3 --- CHOPPER-STABILIZATION TECHNIQUE --- p.13 / Chapter 2.4 --- MIRRORED INTEGRATOR --- p.16 / Chapter 2.5 --- PERFORMANCE METRICS --- p.18 / Chapter 2.5.1 --- SIGNAL TO NOISE RATIO (SNR) --- p.18 / Chapter 2.5.2 --- SIGNAL TO NOISE AND DISTORTION RATIO (SNDR) --- p.19 / Chapter 2.5.3 --- DYNAM IC RANGE --- p.19 / Chapter 2.5.4 --- EFFECTIVE NUMBER OF BITS --- p.19 / Chapter 2.5.5 --- "OVERLOAD LEVER, XOL" --- p.19 / Chapter 2.6 --- CONCLUSION --- p.20 / Chapter CHAPTER 3 --- NON-IDEALITIES IN SYSTEM MODELING --- p.21 / Chapter 3.1 --- CLOCK JITTER --- p.21 / Chapter 3.2 --- NON-IDEAL EFFECT OF OPERATIONAL AMPLIFIER --- p.23 / Chapter 3.2.1 --- FINITE OPEN-LOOP GAIN --- p.23 / Chapter 3.2.2 --- FINITE BANDWIDTH AND SLEW-RATE --- p.24 / Chapter 3.3 --- CAPACITOR RATIO ERROR --- p.26 / Chapter 3.4 --- THERMAL NOISE --- p.27 / Chapter 3.5 --- SWITCH CHARGE INJECTION ERROR --- p.30 / Chapter 3.6 --- CONCLUSION --- p.34 / Chapter CHAPTER 4 --- A CHOPPER-STABILIZED HIGH-PASS DELTA-SIGMA MODULATOR IN 1.8V 0.18MM CMOS --- p.35 / Chapter 4.1 --- STRUCTURE SELECTION --- p.35 / Chapter 4.2 --- SYSTEM MODELING AND PARAMETER SELECTION --- p.38 / Chapter 4.3 --- CIRCUIT IMPLEMENTATION --- p.42 / Chapter 4.3.1 --- OPERATIONAL AMPLIFIER --- p.42 / Chapter 4.3.2 --- QUANTIZER --- p.44 / Chapter 4.3.3 --- FREQUENCY DIVIDER --- p.47 / Chapter 4.3.4 --- OVERALL CIRCUIT --- p.48 / Chapter 4.4 --- LAYOUT IMPLEMENTATION --- p.50 / Chapter 4.4.1 --- LAYOUT SYMMETRIC TECHNIQUE --- p.50 / Chapter 4.4.2 --- CIRCUIT LAYOUT --- p.53 / Chapter 4.4.3 --- FLOOR PLANNING AND TOP LEVEL INTER-CONNECT!ON --- p.56 / Chapter 4.5 --- MEASUREMENT RESULTS --- p.58 / Chapter CHAPTER 5 --- A LOW-POWER CHOPPER-STABILIZED DELTA-SIGMA MODULATOR IN 1.2V0.18MM CMOS --- p.63 / Chapter 5.1 --- STRUCTURE SELECTION --- p.63 / Chapter 5.2 --- SYSTEM MODELING AND PARAMETER SELECTION --- p.67 / Chapter 5.3 --- CIRCUIT IMPLEMENTATION --- p.70 / Chapter 5.3.1 --- OPERATIONAL AMPLIFIER --- p.70 / Chapter 5.3.2 --- QUANTIZER --- p.73 / Chapter 5.3.3 --- LARGE DELAY GENERATION --- p.73 / Chapter 5.3.4 --- OVERALL CIRCUIT --- p.75 / Chapter 5.4 --- SIMULATION RESULTS --- p.77 / Chapter CHAPTER 6 --- DECIMATION FILTER DESIGN --- p.79 / Chapter 6.1. --- THE WHOLE VIEW OF DECIMATION FILTER --- p.79 / Chapter 6.2. --- THE DECIMATION FILTER IN SIMULINK --- p.80 / Chapter 6.2.1 --- SINE FILTER DESIGN --- p.80 / Chapter 6.2.2 --- HALF-BAND FILTER DESIGN --- p.82 / Chapter CHAPTER 7 --- CONCLUSIONS AND FUTURE WORKS --- p.88 / Chapter 7.1. --- CONCLUSIONS --- p.88 / Chapter 7.2. --- FUTURE WORKS --- p.89 / REFERENCES --- p.90 / PUBLICATION --- p.93

CMOS technology scaling has enabled dramatic improvement for digital circuits both in terms of speed and power efficiency. However, most traditional analog-to-digital converter (ADC) architectures are challenged by ever-decreasing supply voltage. The improvement in time resolution enabled by increased digital speeds drives design towards time-domain architectures such as voltage-controlled-oscillator (VCO) based ADCs. The main challenge in VCO-based ADC design is mitigating the nonlinearity of VCO Voltage-to-frequency (V-to-f) characteristics. Achieving signal-to-noise ratio (SNR) performance better than 40dB requires some form of calibration, which can be realized by analog or digital techniques, or some combination. This dissertation proposes a highly digital, reconfigurable VCO-based ADC with lookup-table (LUT) based background calibration based on "split ADC" architecture. Each of the two split channels, ADC "A" and "B", contains two VCOs in a differential configuration. This helps alleviate even-order distortions as well as increase the dynamic range. A digital controller on chip can reconfigure the ADCs' sampling rates and resolutions to adapt to various application scenarios. Different types of input signals can be used to train the ADC’s LUT parameters through the simple, anti-aliasing continuous-time input to achieve target resolution. The chip is fabricated in a 180 nm CMOS process, and the active area of analog and digital circuits is 0.09 and 0.16mm^2, respectively. Power consumption of the core ADC function is 25 mW. Measured results for this prototype design with 12-b resolution show ENOB improves from uncorrected 5-b to 11.5-b with calibration time within 200 ms (780K conversions at 5 MSps sample rate).

Bibliography: leaves 212-223.

In this dissertation, a new ����� A/D converter is presented that is ideally suited for communication applications. It is based on a single-loop single-stage structure, which can realize a high maximum out-of-band quantization noise gain while maintaining stable operation and thus achieve 14-bit resolution at 8 times oversampling. A fifth-order ����� analog-to-digital converter (A/D) has been designed and tested in a 0.18 ��m CMOS process. This is the first single-stage ����� A/D converter reported in the literature that achieves 14-bit resolution at 4 MHz equivalent Nyquist rate with a 1.8-V power supply. / Graduation date: 2002