Les principaux résultats de recherche présentés dans cette thèse de Doctorat concernent la proposition de nouvelles méthodologies de spécifications et de dimensionnement ainsi que des techniques de mise en œuvre de structures de filtrage et de conception d'architectures matérielles reconfigurables pour la sélection numérique des canaux radio dans un contexte de réception multistandard. Les résultats obtenus à l'issue de cette thèse constituent une contribution à un nouvel axe de recherche qui vise à développer de nouvelles technologies pour des équipements radio flexibles, multi-service, multi-standards, multi-bandes, re-configurables mais tout en limitant la complexité de traitement et d'implantation matérielle en vue de réduire d'avantage l'encombrement des équipements portables ainsi que leur consommation d'énergie. Notre première étape d'étude a concerné la définition de structure et de méthode de dimensionnement d'un récepteur radio à conversion directe doté de fonctionnalités large bande et multi-bande. Une méthode a aussi été établie pour déterminer les spécifications des étages de sélection des canaux en tenant compte de la structure de filtrage en cascade, des profils des signaux et interférents radio ainsi que des effets de repliement de spectre. Les résultats de synthèse sur FPGA ont permis de mettre en évidence les performances en terme de qualité de filtrage et d'optimisation des ressources d'implantation matérielle.

A 3D-model consists out of triangles, and in many cases, the amount of triangles are unnecessarily large for the application of the model. If the camera is far away from a model, why should all triangles be there when in reality it would make sense to only show the contour of the model? Mesh decimation is often used to solve this problem, and its goal is to minimize the amount of triangles while still keep the visual representation intact. Having the decimation algorithm being structure aware, i.e. having the algorithm aware of where the important parts of the model are, such as corners, is of great benefit when doing extreme simplification. The algorithm can then decimate large, almost planar parts, to only a few triangles while keeping the important features detailed. This thesis aims to describe the development of a structure aware decimation algorithm for the company Spotscale, a company specialized in creating 3D-models of drone footage.

Global Positioning Systems (GPS) is undergoing stunning changes and upgrades which will enhance the Civil and Military users. This modernization included new satellite signals for Civil and Military purposes which benefits the fundamental signal acquisition and tracking of the GPS receiver. These new signals enable a new family of alternatives for mitigating the ionospheric errors that currently limit the GPS accuracy [16]. A new Civil signal L2 Civil (L2C) was commissioned on the L2 frequency which could have ionospheric error elimination capability, with better cross correlation, Data recovery performance, and threshold tracking. The complex structure of the signal calls for new Acquisition approaches which are implementable with limited computational burden. This thesis proposes an Acquisition methodology to acquire the Code phase offset and Carrier frequency offset of the L2C signal which can be implemented in real time. The algorithm employs a serial code search for Code Phase by retaining the original sampling frequency `fs' and implements a FFT search for carrier frequency offset with a reduced sampling frequency of `fs/M' where `M' is the decimation rate. Multirate Filters are employed for reducing the sampling frequency. After the Acquisition is performed, the values are passed onto the Phase Lock Loop (PLL) and Delay Lock Loop (DLL) to further synchronize the Code Phase and Carrier frequency. The algorithm was tested on a real data set for the performance evaluation of Acquisition and Tracking, and the navigation bits were extracted and the results discussed.

Automatic mesh optimization algorithms suffer from the problem that humans are not uniformly sensitive to changes on different parts of the body. This is a problem because when a mesh optimization algorithm typically measures errors caused by triangle reductions, the errors are strictly geometrical, and an error of a certain magnitude on the thigh of a 3D model will be perceived by a human as less of an error than one of equal geometrical significance introduced on the face. The partial solution to this problem proposed in this paper consists of detecting the faces of the 3D assets to be optimized using conventional, existing 2D face detection algorithms, and then using this information to selectively and automatically preserve the faces of 3D assets that are to be optimized, leading to a smaller perceived error in the optimized model, albeit not necessarily a smaller geometrical error. This is done by generating a set of per-vertex weights that are used to scale the errors measured by the reduction algorithm, hence preserving areas with higher weights. The final optimized meshes produced by using this method is found to be subjectively closer to the original 3D asset than their non-weighed counterparts, and if the input meshes conform to certain criteria this method is well suited for inclusion in a fully automatic mesh decimation pipeline

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International Telemetering Conference Proceedings / October 25-28, 1993 / Riviera Hotel and Convention Center, Las Vegas, Nevada / With the advancement in speed and complexity of Application Specific Integrated Circuits (ASICs), Digital Signal Processing (DSP) algorithms can now be used to achieve fully programmable, multiple channel demodulation of Frequency Modulation (FM) multiplexes. This paper describes the DSP algorithms and ASIC implementation used in the design of a digital FM demodulator system. Each digital demodulator has programmable subcarrier frequency demodulation to 4 MHz, programmable digital output filtering, and tape speed compensation (TSC). The demodulator output is available in both digital form for direct computer interface and in analog form for conventional analysis.

The aim of this thesis is to implement flexible interpolators and decimators onField Programmable Gate Array (FPGA). Interpolators and decimators of differentwordlengths (WL) are implemented in VHDL. The Farrow structure is usedfor the realization of the polyphase components of the interpolation/decimationfilters. A fixed set of subfilters and adjustable fractional-delay multiplier valuesof the Farrow structure give different linear-phase finite-length impulse response(FIR) lowpass filters. An FIR filter is designed in such a way that it can be implementedfor different wordlengths (8-bit, 12-bit, 16-bit). Fixed-point representationis used for representing the fractional-delay multiplier values in the Farrow structure. To perform the fixed-point operations in VHDL, a package called fixed pointpackage [1] is used. A 8-bit, 12-bit, and 16-bit interpolator are implemented and their performancesare verified. The designs are compiled in Quartus-II CAD tool for timing analysisand for logical registers usage. The designs are synthesised by selecting Cyclone IVGX family and EP4X30CF23C6 device. The wordlength issues while implementingthe interpolators and decimators are discussed. Truncation of bits is required inorder to reduce the output wordlength of the interpolator and decimator.

The master thesis is based upon a new type of linear-phase Nyquist finitie impulse responseinterpolator and decimator implemented using a tree-structure. The tree-structure decreasesthe complexity, considerably, compared to the ordinary single-stage interpolator structure.The computational complexity is comparable to a multi-stage Nyquist interpolator structure,but the proposed tree-structure has slightly higher delay. The tree-structure should still beconsidered since it can interpolate with an arbitrary number and all subfilters operate at thebase rate which is not the case for multi-stage Nyquist interpolators.

Reducing the number of vertices in a mesh is a problem that if solved correctly can save the user a lot of time in the entire process of handling the model. Most of the solutions today are focused on reducing the mesh in one big step by running a separate application. The goal of this implementation is to bring the reduction application into the users workspace as a plugin. Many of the modellers in the various computer graphics industries use Autodesk Maya the plugins intention is to create a efficient tool which also give the modellers as much freedom as possible without the need to ever leave Mayas workspace. During the process the possible issues and solutions of creating this tool in Maya will also examined to help introduce the process of creating a tool for Maya. This plugin has the potential to improve on the existing reduction tool in Maya by giving the user more options and a more exact solution.

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