This thesis is to deal with the saturation problem arisen from the integrator accumulation in the loop of the sigma-delta analog-to-digital converter. Signal passes through the accumulation of several integrators in the high-order sigma-delta analog-to-digital converter, it tends to result in saturation problem in the output of integrator. This phenomenon is prominent especially in implementation. Unable to correctly propagate signal to the next integrator stage, thus, causes the analog-to-digital converter create incorrect result. Accordingly, this thesis proposes a new anti-windup scheme by means of sliding mode control to tackle the saturation problem. We have successfully set up a criterion for the selection of parameters of the sigma-delta analog-to-digital converter to prevent the integrators from saturation. After extensive simulation and experiment, it can significantly improve the ensemble of the sigma-delta analog-to-digital modulator.

The main goal of this thesis is to study the saturation problem arisen from the integrator in a sigma- delta analog- to- digital modulator , especially when the order of the circuit is higher than two .Signal passes through each stage of integrators yield saturation problem. This situation will miss some part of messages .Unable to deliver datas accurately to next stage of the integrator , the output digital signals will be incorrect and can't be recovered to original analog signals . Hence, this thesis proposes an anti-wind-up method by taking sliding mode control theory to avoid integrator saturation. After that, we are going to design and implement two third order sigma-delta modulators based on this method. Simulation and experiment results show the validity of the method and the significant improvement of avoiding saturation problem, and guarantee the designed circuits can translate signals to terminal accurately .

Denna avhandling presenterar en undersökning av orsakerna och effekterna av timingosäkerhet i Sigma-Delta Analog-Digital-Omvandlare, med speciellt fokus på Sigma-Delta av den switchade kapacitanstypen. Det undersökta området för orsakerna till timingosäkerhet är digital klockgenerering och området för effekterna är sampling. Upplösningsnivån på analysen i detta arbete börjar på beteendenivå och slutar på transistornivå. Samplingskretsen är den intuitiva komponenten att söka i efter orsakerna till effekterna av timing-osäkerhet i en Analog-Digital-Omvandlare eftersom transformationen från reell tid till digital tid sker i samplingskretsen. Därför har prestandaeffekterna av timingosäkerhet i den typiska samplingskretsen för switchad kapacitans Sigma-Delta Analog-Digital-Omvandlare analyserats utförligt, modellerats och beskrivits i denna avhandling. Under analysprocessen har idéer om förbättrade samplingskretsar med naturlig tolerans mot timing-osäkerhet utvecklats och analyserats, och presenteras även. Två typer av förbättrade samplingstopologier presenteras: parallelsamplern och Sigma-Delta-samplern. Den första erhåller tolerans mot timing-osäkerhet genom att utnyttja ett teorem inom statistiken medan den andra är tolerant mot timing-osäkerhet p.g.a. spektral formning som trycker ut brus ur signalens frekvensband. Digital klockgenerering är ett fundamentalt steg i genereringen av multipla klocksignaler som behövs t.ex. i switchade kapacitansversioner av Sigma-Delta Analog-Digital-Omvandlare. Klockgeneratorkretsarna konverterar en tidsreferens, d.v.s. en klocksignal, som vanligen kommer från en faslåst loop till multipla tidsreferenser. De två typerna av klockgenereringskretsar som behandlas i denna avhandling används för att skapa två icke-överlappande klockor från en klocksignal. Processen som undersökts och beskrivits är hur matningsspänningsbrus och substratbrus omvandlas till timing-osäkerhet då en referenssignal passerar genom en av ovannämnda klockgenereringskretsar. Resultaten i denna avhandling har erhållits genom olika analystekniker. Modelleringarna och beskrivningarna har utförts från ett matematiskt och fysikaliskt perspektiv. Detta har fördelen av att kunna förutsäga prestandainfluenser som olika kretsparametrar har utan att behöva utföra datorsimuleringar. Svårigheterna med den matematiska och fysikaliska modelleringen är balansgången mellan olöslighet och överförenkling som måste hittas. Den andra infallsvinkeln är användandet av datorbaserade simuleringsverktyg både för beskrivnings- och verifieringsändamål. Simuleringsverktygen som använts är MATLAB och Spectre/Cadence. Som nämnts har deras syfte varit både som modell- och beskrivningsverifiering och även som ett sätt att erhålla kvantitativa resultat. Generellt talat bryter simuleringsverktyg den mentala kopplingen mellan resultat och diverse kretsparametrar och det kan vara svårt att uppnå en solid prestandaförståelse. Dock är det ibland bättre att erhålla ett prestandamått utan full förståelse än inget mått alls. / This dissertation presents an investigation of the causes and effects of timing uncertainty in Sigma-Delta Analog-to-Digital Converters, with special focus on the switched-capacitor Sigma-Delta type. The investigated field for cause of timing uncertainty is digital clock generation and the field for effect is sampling. The granularity level of the analysis in this work begins at behavioral level and finishes at transistor level. The sampling circuit is the intuitive component to look for the causes to the effects of timing uncertainty in an Analog-to-Digital Converter since the transformation from real time to digital time takes place in the sampling circuit. Hence, the performance impact of timing uncertainties in a typical sampling circuit of a switched-capacitor Sigma-Delta Analog-to-Digital Converter has been thoroughly analysed, modelled, and described in this dissertation. During the analysis process, ideas of improved sampling circuits with inherent tolerance to timing uncertainties were conceived and analysed, and are also presented. Two cases of improved sampling topologies are presented: the Parallel Sampler and the Sigma- Delta sampler. The first obtains its timing uncertainty tolerance from taking advantage of a theorem in statistics whereas the second is tolerant against timing uncertainties because of spectral shaping that effectively pushes the in-band timing noise out of the signal band. Digital clock generation is a fundamental step of generating multiple clock signals that are needed for example in switched-capacitor versions of Sigma-Delta Analog-to-Digital Converters. The clock generation circuitry converts a single time reference, i.e. a clock signal, usually coming from a phase-locked loop into multiple time references. The two types of clock-generation circuits that are treated in this dissertation are used to create two nonoverlapping clocks from a single clock signal. The process that has been investigated and described is how power-supply noise and substrate noise transforms into timing uncertainty when a reference signal is passed through one of the aforementioned clock generation circuits. The results presented in this dissertation have been obtained using different analysis techniques. The modelling and descriptions have been done from a mathematical and physical perspective. This has the benefit of predicting the performance impact by different circuit parameters without the need for computer based simulations. The difficulty with the mathematical and physical modelling is the balance that has to be found between intractability and oversimplification. The other angle of approach has been the use of computer based simulations for both description and verification purposes. The simulation tools that have been used in this work are MATLAB and Spectre/Cadence. As mentioned, their purpose has been both for model and description verification and also as a means of obtaining result metrics. Generally speaking, simulation tools mentally decouple the result from the various circuit parameters and reaching a solid performance understanding can be difficult. However, obtaining a performance metric without full comprehension can at times be better than having no metric at all. / QC 20100921

Abstract The goal of this dissertation was to study and model the settling transient response of switched-capacitor (SC) circuit, which is the most important building block of Analog-to-Digital converters (ADCs), and to improve the settling performance of the SC circuit implemented in ADC in CMOS technology. In the design of the SC circuit, there are common obstacles in obtaining a precise and fast settling with low power consumption. The main contribution of this thesis is to speed up different SC circuits without adding extra power consumption or to achieve the required settling precision with low power consumption. Two solutions to reduce the power consumption of SC integrators in sigma-delta (SD) ADCs were designed and verified by simulations. These implementations are based on the passive charge redistribution technique by injecting a precalculated open-loop charge in the output of the first integrator. The injected charge was implemented either by a continuous function of the input and feedback voltages or by quantizing to three levels. In both cases, the idea is to minimize the initial transient voltage in the input of the first OTA and hence bypass the slewing of the OTA. Another approach was proposed for the traditional SC residue circuit of the pipeline ADC, where a load capacitor is connected to the output during the evaluation phase. Here, a pre-charge of the load capacitance can be used. One proposed implementation is called the continuously controlled pre-charged technique. It pre-charges the load capacitor to the proper voltage during the previous phase, connects the pre-charged load capacitor to the output of the OTA during the evaluation phase, and hence pulls the charge sharing so that the initial input step of the OTA is instantaneously minimized. The other implementation called the minimal pre-charged method implemented for the SC residue circuit of the pipeline ADC is to simply pre-charge the load capacitor with the fixed existing voltage, minimized the spread of the initial input voltage. This proposed technique did not require any additional active components. / Tiivistelmä Kytkettyihin kapasitansseihin (SC-tekniikka) perustuvat vahvistimet ovat CMOS-tekniikkaan perustuvien analogia-digitaalimuuntimien (AD-muunnin) tärkeimpiä osia. Tämän väitöstyön tavoitteena oli tutkia ja mallittaa SC-tekniikkaan perustuvien vahvistinpiirien asettumisaikaa, ja etsiä piiriteknisiä keinoja asettumisajan nopeuttamiseksi. SC-piirien suunnittelun suurimpia ongelmia on saavuttaa tarkka ja nopea asettuminen mahdollisimman pienellä tehonkulutuksella. Tämän työn päätuloksina on joukko keinoja, joilla voidaan nopeuttaa SC-kytkettyjen vahvistimien asettumista ilman että niiden tehonkulutusta lisätään, tai saavuttaa aiempi suorituskyky pienemmällä tehonkulutuksella. Menetelmät perustuvat siihen, että SC-piirin passiivista varausjakautumista ohjataan niin, että vahvistimen tulosolmussa oleva transientti minimoituu, jolloin vahvistin ei ajaudu virtarajoitteiselle toiminta-alueelle, vaan sen asettuminen nopeutuu merkittävästi. Sigma-delta-tyyppiset AD-muuntimet koostuvat SC-integraattoreista, ja näiden asettumisen nopeuttamiseen kehitettiin ja varmennettiin simuloiden kaksi tapaa. Varauksen jakautumista autettiin syöttämällä erillisellä varauspumpulla transkonduktanssivahvistimen lähtösolmuun tietty, integraattorin tilasta ja tuloista riippuva varaus. Tällöin vahvistimen tulossa näkyvä alkutransientti pienenee, ja vahvistin ei ajaudu virtarajoitteiselle toiminta-alueelleen, jolloin sen asettumisvirhe pienenee merkittävästi. Varausinjektio toteutettiin kahdella eri tavalla: laskemalla tarvittava varaus joko jatkuvana funktiona tulosignaaleista, tai approksimoimalla sitä muutamalla diskreetillä tasolla. Pipeline-tyyppisissä AD-muuntimissa peruslohko koostuu SC-kytketystä vahvistimesta, jonka kuormakapasitanssi on kytkettynä vahvistimen lähtöön asettumisen aikana. Tämän kapasitanssin esivaraaminen sopivasti tarjoaa hyvin yksinkertaisen keinon ohjata varausjakautumista niin, että vahvistimen tulossa oleva transientti saadaan minimoitua ja toiminta virtarajoitteisessa moodissa vältettyä. Tässäkin tapauksessa kehitettiin ja varmennettiin kaksi vaihtoehtoista toteutusta. Ensimmäisessä kuormakapasitanssin esivarausjännite lasketaan tulosuureiden jatkuvana funktiona erillisellä summausvahvistimella. Toisessa, hyvin minimalistisessa ratkaisussa esivaraukseen käytetään kolmea käytettävissä olevaa kiinteää jännitettä. Tämä menetelmä ei vaadi lainkaan ylimääräisiä aktiivikomponentteja.