The main goal of this thesis is to study the saturation problem arisen from the integrator in a sigma- delta analog- to- digital modulator , especially when the order of the circuit is higher than two .Signal passes through each stage of integrators yield saturation problem. This situation will miss some part of messages .Unable to deliver datas accurately to next stage of the integrator , the output digital signals will be incorrect and can't be recovered to original analog signals . Hence, this thesis proposes an anti-wind-up method by taking sliding mode control theory to avoid integrator saturation. After that, we are going to design and implement two third order sigma-delta modulators based on this method. Simulation and experiment results show the validity of the method and the significant improvement of avoiding saturation problem, and guarantee the designed circuits can translate signals to terminal accurately .