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Using IEEE 1500 for wafer testing of TSV Based 3D integrated circuits

The potential end of Moore's law has caused the semiconductor industry to investigate 3D integrated circuits as a way to continue to increase transistor density. Solutions must be put in place to allow each 3D IC die layer to be tested thoroughly on its own at wafer level to unsure adequate yield on assembled 3D devices. This paper details the testability of a 3D implementation of the Open Cores or1200 architecture. IEEE 1500 is used to signi cantly improve wafer level testability of the 3D IC die layers while maintaining a low test pin count requirement. / text

Identiferoai:union.ndltd.org:UTEXAS/oai:repositories.lib.utexas.edu:2152/ETD-UT-2011-12-4471
Date24 February 2012
CreatorsUgland, Ryan A.
Source SetsUniversity of Texas
LanguageEnglish
Detected LanguageEnglish
Typethesis
Formatapplication/pdf

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