With sub-micron silicon processing technology reaching under 30nm, it becomes more difficult for integrated circuits to achieve higher integration through the scaling down of the transistor size. Three-dimensional integrated circuit (3D-IC) technology stacks multiple dies together and connects them using through-silicon vias (TSVs). This is a low cost and highly efficient way to increase integration. TSVs and stacked dies are two major features of the 3D-IC technology. However, the stacked structures using TSV interconnects induce concerns in reliability such as TSV strain effect, heat problem, and TSV coupling at high frequency, etc. The reliability concerns need to be carefully addressed before 3D-IC technologies can be widely adopted by the industry. Many studies have been carried out in this field, but there has not been much significant work done for testing electrical, mechanical and thermal issues of the 3D-IC technology simultaneously on a single test chip. In this work, a test chip including various test structures was designed to study and analyze these issues in a 3D-IC technology. An accurate resistance and capacitance (RC) model of the TSV for low frequency design was developed, high frequency electrical performance of the TSVs was characterized, coupling between TSVs was modeled, and the stress effect and the heat dissipation method were analyzed in the 3D-IC technology. The TSV model could be added to the design kit for future 3D-IC design and other results could be used to improve the reliability of 3D-IC designs and optimize the performance.

This paper proposes a multitier multilevel TSV diagnosis scheme for 3D ICs to achieve interconnect reliability and yield with targets of interconnect faults under stuck-at and open fault models. This scheme takes advantage of previous work of IEEE 1500 compatible interconnect test and diagnosis methods, and further develop a TSV detection and diagnosis method for 3D circuits. An interconnect diagnosis scheme based on the oscillation ring (OR) test methodology for 3D systems-on-chip (SOC) designs with heterogeneous cores is proposed. The large number of test rings in the SOC design, however, significantly complicates the interconnect diagnosis problem. In this paper, the diagnosability of an interconnect structure is first analyzed then a fast diagnosability checking algorithm and an efficient diagnosis ring generation algorithm are proposed. It is shown in this paper that the both vertical and horizontal ring generation algorithm achieves the maximum detectability for any interconnect.

Taura syndrome virus (TSV), the epidemic agent of Taura syndrome (TS), was tentatively classified in the family Dicistroviridae, caused disastrous losses with high mortality rates from 60 to >90% of affected pond-cultured Litopenaeus vannamei. The amino acid sequence alignments of ORF1 revealed sequence motifs characteristic of a helicase, a protease and an RNA-dependent RNA polymerase, similar to the non-structural proteins of picornavirus, suggesting perhaps a similar to picornavirus polyprotein processing. Proteolytic processing of the TSV polyprotein and protease is still unclear. In order to further understand the role of protease interaction with polyprotein, several clones were constructed. In this study, we constructed several clones that expressed the TSV virus coat protein(VP-polyprotein)¡]pTSVVP¡^, putative 3C protease¡]pTSV3C¡^, protease¡ÏRdRp-polyprotein(pET3CD) and both VP+3C proteins(pTSVVP3C) in E. coli. The VP-polyprotein band was excised from SDS-polyacrylamide gels and electroeluted for antibody production in mice. Processing of the VP-polyprotein by 3C protease was carried out in the in vitro co-transcription/translation system and detected by Western blot. The results showed there were protein bands corresponding to the sizes of VP2+VP1 and VP1+VP3 indicating that the processing might have been partial or incomplete.

A series of studies were conducted as part of my dissertation research on certain diseases of farmed penaeid shrimp and on strategies that might be applied to manage these diseases. These studies focused on the development and application of management for four shrimp diseases (TSV, YHV, WSSV and NHP) in the white shrimp Penaeus vannamei through different strategies. The studies focused on efforts to identify a new strain of Taura syndrome virus (TSV), and the prevention or mitigation of infection by Yellow Head Disease (YHD), White Spot Disease (WSD), and Necrotizing Hepatopancreatitis (NHP). The new strain of TSV reported in this study is among the most pathogenic strains discovered to date. Disease management strategies investigated include the prevention of YHD in the Americas by pre-exposing Specific-Pathogen-Free (SPF) Penaeus vannamei to TSV. The other strategy investigated involved the use of a prototype "vaccine" that binds to the specific shrimp cell receptors and thus, prevents WSSV from establishing an infection. The last strategy attempted to elucidate the reasons for the very low prevalence of NHP in commercial shrimp ponds in Colombia. It was found that through establishment of a breeding program in which shrimp were selected for resistance to TSV infection, Colombian shrimp farmers also, but indirectly, selected for resistance to NHP.

A test chip design is presented for the characterization of process variations and Through Silicon Via (TSV) induced mechanical stress in 3D integrated circuits. The chip was de- signed, layed-out, and taped-out for fabrication in a 130nm Tezzaron/GlobalFoundries process through CMC microsystems. The test chip takes advantage of the architecture of 3D ICs to split its test structure onto the two tiers of the 3D IC, achieving a device array density of 40.94 m2 per device. The design also has a high spatial resolution and measurement delity compared to similar 2D variation characterization test structures. Background leakage subtraction and radial ltering are two techniques that are ap- plied to the chip's measurements to reduce its error further for subthreshold device current measurements and stress-induced mobility measurements, respectively. Experimental mea- surements are be taken from the chip using a custom PCB measurement setup once the chip has returned from fabrication.

The potential end of Moore's law has caused the semiconductor industry to investigate 3D integrated circuits as a way to continue to increase transistor density. Solutions must be put in place to allow each 3D IC die layer to be tested thoroughly on its own at wafer level to unsure adequate yield on assembled 3D devices. This paper details the testability of a 3D implementation of the Open Cores or1200 architecture. IEEE 1500 is used to signi cantly improve wafer level testability of the 3D IC die layers while maintaining a low test pin count requirement. / text

Continuous downscaling of transistor size has been the major trend of the semiconductor industry for the past half century. In recent years, however, fundamental physical limits to continued downscaling were encountered. In order to overcome these limits, the industry experimented --- and continues to experiment --- with many new materials and architectures. Non-invasive, in-line methods of characterizing critical properties of these structures are in demand. This dissertation develops optical second-harmonic generation (SHG) to characterize performance-limiting defects, band alignment or strain distribution in four advanced electronic material systems of current interest: (1) Hot carrier injection (HCI) is a key determinant of the reliability of ultrathin silicon-on-insulator (SOI) devices. We show that time-dependent electrostatic-field-induced SHG probes HCI from SOI films into both native and buried oxides without device fabrication. (2) Band offsets between advanced high-k gate dielectrics and their substrates govern performance-limiting leakage currents, and elucidate interfacial bond structure. We evaluate band offsets of as-deposited and annealed Al₂O₃, HfO₂ and BeO films with Si using internal photoemission techniques. (3) Epi-GaAs films grown on Si combine the high carrier mobility and superior optical properties of III-V semiconductors with the established Si platform, but are susceptible to formation of anti-phase boundary (APB) defects. We show that SHG in reflection from APB-laden epi-films is dramatically weaker than from control layers without APBs. Moreover, scanning SHG images of APB-rich layers reveal microstructure lacking in APB-free layers. These findings are attributed to the reversal in sign of the second-order nonlinear optical susceptibility [chi]⁽²⁾ between neighboring anti-phase domains, and demonstrate that SHG characterizes APBs sensitively, selectively and non-invasively. (4) 3D integration --- i.e. connecting vertically stacked chips with metal through-Si-vias (TSVs) --- is an important new approach for improving performance at the inter-chip level, but thermal stress of the TSVs on surrounding Si can compromise reliability. We present scanning SHG images for different polarization combinations and azimuthal orientations that reveal the sensitivity of SHG to strain fields surrounding TSVs. Taken together, these results demonstrate that SHG can identify performance-limiting defects and important material properties quickly and non-invasively for advanced MOSFET device applications. / text

<p>Three-dimensional (3D) stacking using through-silicon vias (TSVs) promises higher integration levels in a single package, keeping pace with Moore's law. TSVs are small copper or tungsten vias that go vertically through the substrate of a die and provide vertical interconnects to a die stacked on top. TSV-based interconnects have benefits in terms of performance, interconnect density, and power efficiency.</p><p>Testing has been identified as a showstopper for volume manufacturing of 3D-stacked integrated circuits (3D ICs). A number of challenges associated with 3D test need to be addressed before 3D ICs can become economically viable. This dissertation provides solutions to new challenges related to 3D test content, test access, diagnosis and debug.</p><p>Test content specific to 3D ICs targets defect that occur during TSV manufacturing and stacking process. One example is the effect of thermo-mechanical stress due to TSV fabrication process on the surrounding logic gates. In this dissertation, we analyze these effects and their consequences for delay testing. We provide quantitative results showing that the use of TSV-stress oblivious circuit models for test generation leads to considerable reduction in delay-test quality. We propose a test flow that uses TSV-stress aware circuit models to improve test quality.</p><p>Another example of 3D-specific test challenge is the testability of TSVs. In this dissertation, we focus on TSV test prior to die bonding, as access to TSVs is limited at this stage. We propose a non-invasive method for pre-bond TSV test that does not require TSV probing. The method uses ring oscillators and duty-cycle detectors in order to detect variations in propagation delay of gates connected to a single-sided TSV. Based on the measured variations, we can diagnose the TSV and predict the size of resistive-open and leakage faults using a regression model based on artificial neural networks. In addition, we exploit different voltage levels to increase the robustness of the test method.</p><p>In order to efficiently deliver test content to structures under test in a 3D stack, 3D design-for-test (DfT) architectures are needed. In this dissertation, we discuss existing 3D-DfT architectures and their optimization. We propose an optimization approach that takes uncertainties in input parameters into account and provides a solution that is efficient in the presence of input-parameter variations and minimizes test time, therefore reducing test cost.</p><p>Post-silicon debug is a major challenge due to continuously increasing design complexity. Traditional debug methods using signal tracing suffer from the limited capacity of on-chip trace buffers that only allow for signal observation during a short time window. This dissertation proposes a low-cost debug architecture for massive signal tracing in 3D-stacked ICs with wide-I/O DRAM dies. The key idea is to use available on-chip DRAM for trace-data storage, which results in a significant increase of the observation window compared to traditional methods that use trace buffers. In addition, the proposed on-chip debug circuitry can identify erroneous segments of observed data by using compact signatures that are stored in the DRAM a priori. Only failing intervals are off-loaded from a temporary trace buffer into DRAM, allowing for a more efficient use of the memory, resulting in a larger observation window.</p><p>In summary, this dissertation provides solutions to several challenges related to 3D test and debug that need to be addressed before volume manufacturing of 3D ICs can be viable.</p> / Dissertation

Kuwait is an arid country situated at the head of the Arabian Gulf and its water resources can be classified into three significant types: (1) natural (groundwater) and (2) artificial (desalinated sea water and treated wastewater). In the absence of surface water bodies, groundwater constitutes the most important natural water resource in Kuwait with TDS [less than or equal to]10000 mg/L in central and south Kuwait. Only in the north can one find fresh water lenses. Brackish groundwater are used for irrigation, landscaping, construction work, non-potable use in households and mixing with desalinated water up to 10%, to make it potable. The occurrence of usable groundwater is limited to the Kuwait Group and Dammam Formation. Due to over-pumping of groundwater over the last few years, the levels and quality of groundwater are deteriorating. Kuwait is described as the poorest country in terms of water availability (UN World Water-2003). The current rates of water consumption are very high, with 459.6 L/C/d and almost 91 L/C/d for fresh and brackish water, respectively. The water budget of the water resources, represented as percentages is 59% from desalination sea water plants, 32% from groundwater with the possibility to increase the use of this resource and 9% from waste water reuse plants. Although Kuwait does not have any surface water, but it depends on technology to produce water recourses to meet the demand. The best solution for solve the issues of declining water levels and increasing salinity is artificial recharge. Artificial recharge has been applied in Kuwait in different groundwater fields since the 1980s. In addition, the available surface storage capacity of 11.7 Mm³ freshwater is sufficient to meet demand for about 7 days. So, Aquifer storage and recovery (ASR) can be used to store the water in aquifers instead of surface storage. ASR entails storing water in aquifers during wet times and recovering the water from the same well during drought times. Surface storage needs construction resources and vast land. In contrast, storing water in aquifer storage does not need that and it can decrease salinity and keep the water table constant. The water availability for artificial recharge can come from desalination and wastewater plant. The capacity and production of desalination plants are 1.425Mm³/day (525.125Mm³/yr) and 1.31Mm³/day (478.15 Mm³/yr), respectively from 5 stations. The excess capacity is 115000 m³ per day and could reach 290000 m³ per day in the winter season. Wastewater treatment plants produce from 3 plants around 0.337 Mm³/day (123.342 Mm³/yr) and the newest plant (operating by RO system) produces 0.32 Mm³/day (117.12 Mm³/yr) and will reach 0.643 Mm³/day (235.338 Mm³/yr) in 2015. The water produced from wastewater treatment plants has good quality and can be used for irrigation, greening enhancement, landscaping, recreation (artificial river and lakes) and artificial recharge. Also, using water treated for artificial recharge will improve the quality of injected water that has been successfully treated with soil aquifer treatment technology. Groundwater pumping is 200 Mm³ annually and is likely to reach 280 Mm³ in the future. This research will explore and create a database for water resource by GIS software using its tool to select and display suitable areas for ASR operation. Artificial recharge in Kuwait has used the concept of injection and recovery of water in one cycle, while here we will apply the multi-cycle concept to avoid increasing the piezometric head and clogging the porous media. The injected water will be from wastewater treatment plants with a TDS content of less 500 ppm and the TDS of recovered water in each well less than 1500 ppm. Moreover, there are criteria for selecting a domain for artificial recharge, for example, moderate transmissivity, The TDS of the aquifer should not exceed 5000 ppm, and the horizontal and vertical hydraulic gradient should be as small as possible and close to the stations suppler and demand center. The success of artificial recharge will depend on the recovery efficiency (RE) in every cycle which will increase if artificial recharge done in the correct way. The RE increases with a decrease in time between the stopping of injection and the starting of the recovery operation. Aquifer storage and recovery can play an important role as sustainability tool to resolve water resource problems, improving water quality, better than surface water storage since it minimizes construction of new infrastructure and uses that cost to initiate new desalination or waste water plants. At the end of this research we will have demonstrated the concept of the process of ASR including the volume and time for injection and recovery of water in multi-cycles and in different suitable sites. / text

A test chip design is presented for the characterization of process variations and Through Silicon Via (TSV) induced mechanical stress in 3D integrated circuits. The chip was de- signed, layed-out, and taped-out for fabrication in a 130nm Tezzaron/GlobalFoundries process through CMC microsystems. The test chip takes advantage of the architecture of 3D ICs to split its test structure onto the two tiers of the 3D IC, achieving a device array density of 40.94 m2 per device. The design also has a high spatial resolution and measurement delity compared to similar 2D variation characterization test structures. Background leakage subtraction and radial ltering are two techniques that are ap- plied to the chip's measurements to reduce its error further for subthreshold device current measurements and stress-induced mobility measurements, respectively. Experimental mea- surements are be taken from the chip using a custom PCB measurement setup once the chip has returned from fabrication.