Physical scaling limits of microelectronic devices and the need to improve electrical performance have driven significant research and development into 3D architecture. The development of die stacks in first level packaging is one of the more viable short-term options for improved performance. Placement of memory die above or below processors in a traditional flip chip C4 package with through-silicon vias (TSVs) has significant benefits in reducing data and power transmission paths. However, with the electrical performance benefits come great thermal and mechanical challenges. There are two key objectives for this work. The first is understanding of the die-die interface resistance, R[subscript dd], composed of the back end of line (BEOL) layers and micro-C4 interconnects. The interfacial resistance between BEOL material layers, the impact of TSVs and the impact of strain on R[subscript dd] are subtopics. The second key objective is the understanding of package thermal and mechanical behavior under operating conditions, such as local thermal disturbances. To date, these topics have not been adequately addressed in the literature. It is found that R[subscript dd] can be affected by TSVs, and that the interfacial contributions predicted by theoretical sub-continuum models can be significantly different than measurements. Using validated finite element models, the significance of the power distribution and R[subscript dd] on the temporal responses of 2D vs. 3D packages is highlighted. The results suggest local thermal hotspots can greatly exacerbate the thermal penalty due to the R[subscript dd] and that no peaks in stress arise in the transient period from power on to power off. / text

As nanometer Very Large Scale Integration (VLSI) demands more transistor density to fabricate multi-cores and memory blocks in a limited die size, many researches have been performed to keep Moore's Low in two different ways: 2D geometric shrinking and 3D vertical wafer stacking. For the geometric shrinking, nano patterning with 193nm lithography equipment is one of the most fundamental challenges beyond 22nm while the next-generation lithography, such as Extreme Ultra-Violet (EUV) lithography still faces tremendous challenges for volume production in the near future. As a practical solution, Double Patterning Lithography (DPL) has become a leading candidate for sub-20nm lithography process. Another approach for multi-core integration is 3D wafer stacking with Through Silicon Via (TSV). Computer-Aided-Design (CAD) approaches to enable robust DPL and TSV technology are the main focus of this dissertation. DPL poses new challenges for overlay and layout decomposition. Therefore, overlay induced variation modeling and efficient decomposition for better manufacturability are in great demand. Since the variation of metal space caused by overlay results in coupling capacitance variation, we first model metal spacing variation with individual overlay sources. Then, all overlay sources are considered to determine the worst timing with coupling capacitance variation. Non-parallel pattern caused by overlay is converted to parallel one with equivalent spacing having the same delay to be applicable of a traditional RC extraction flow. Our experiments show that the delay variation due to overlay in DPL can be up to 9.1%, and well decomposed layout can reduce the variability. For DPL layout decomposition, we propose a multi-objective and flexible framework for stitch minimization, balanced density, and overlay compensation, simultaneously. We use a graph theoretic algorithm for minimum stitch insertion and balanced density. Additional decomposition constraints for overlay compensation are obtained by Integer Linear Programming (ILP). Robust contact decomposition can be obtained with additional constraints. With these constraints, global decomposition is performed using a modified Fiduccia-Mattheyses (FM) graph partitioning algorithm. Experimental results show that the proposed framework is highly scalable and fast: we can decompose all 15 benchmark circuits in five minutes in a density balanced fashion, while an ILP-based approach can finish only the smallest five circuits. In addition, we can remove more than 95% of the timing variation induced by overlay for tested structures. Three-dimensional integration has new manufacturing and design challenges such as device variation due to TSV induced stress and timing corner mismatch between different stacked dies. Since TSV fill material and silicon have different Coefficients of Thermal Expansion (CTE), TSV causes silicon deformation due to different temperatures at chip manufacturing and operating. Therefore, the systematic variation due to TSV induced stress should be considered for robust 3D IC design. We propose systematic TSV stress aware timing analysis and show how to optimize layout for better performance. First, a stress contour map with an analytical radial stress model is generated. Then, the tensile stress is converted to hole and electron mobility variations depending on geometric relations between TSVs and transistors. Mobility variation aware cell library and netlist are generated and incorporated in an industrial timing engine for 3D-IC timing analysis. TSV stress induced timing variations can be as much as 10% for an individual cell. As an application for layout optimization, we can exploit the stress-induced mobility enhancement to improve timing on critical cells. We show that stress-aware perturbation could reduce cell delay by up to 14.0% and critical path delay by 6.5% in our test case. Three-dimensional Clock Tree Synthesis (3D CTS) is one of the main design difficulties in 3D integration because clock network is spreading over all tiers. In 3D CTS, timing corner mismatch between tiers is caused because each tier is manufactured in independent process. Therefore, inter-die variation should be considered to analyze and optimize for paths spreading over several tiers in 3D CTS. In addition, mobility variation of a clock buffer due to stress from TSV can cause unexpected skew which degrades overall chip performance. Therefore, we propose clock period optimization to consider both timing corner mismatch and TSV induced stress. In our experiments, we show that our clock buffer tier assignment reduces clock period variation up to 34.2%, and the most of stress-induced skew can be removed by our stress-aware CTS. Overall, we show that performance gain can be up to 5.7% with the proposed CTS algorithm. As technology scaling continues toward 14nm and 3D-integration, this dissertation addresses several key issues in the design-manufacturing interface, and proposes unified analysis and optimization techniques for effective design and manufacturing integration. / text

L'évolution des nœuds technologiques dans l'industrie des semi-conducteurs se traduit de nos jours, dans le domaine des radiofréquences, par une miniaturisation des front-ends et une amélioration des performances électriques des émetteurs-récepteurs à des fréquences de plus en plus hautes. Cette évolution a conduit à la diversification des applications en bandes millimétriques (30 – 300 GHz) dans les secteurs des télécommunications, du divertissement multimédia, de l'automobile et de la sécurité. Plus particulièrement, le secteur des télécommunications connaît aujourd'hui une réelle révolution avec la création de nouveaux standards pour les liens sans-fil millimétriques à courte portée (comme WiGiG et IEEE 802.11ad) et l'apparition de nouvelles architectures basées sur des liaisons point-à-point qui constitueront dans les prochaines années la colonne vertébrale de la cinquième génération des réseaux mobiles. Dans le cadre de ces travaux de thèse, un intérêt particulier sera porté sur les modules intégrés sans fils et à faible consommation opérant dans la bande 57 – 66 GHz (dite généralement 60 GHz). A ces fréquences, la longueur d'onde en espace libre est comparable aux dimensions caractéristiques des boitiers standards utilisés pour l'encapsulation des transceivers. Il devient donc envisageable d'intégrer les antennes ainsi que d'autres composants passifs directement dans l'empilement technologique du circuit ou dans le boitier. Cette nouvelle génération de dispositifs électroniques, destinés au marché des terminaux portables, introduit de nouveaux défis en termes de performances électriques, de fiabilité mécanique, de coût et de possibilités d'industrialisation. Le packaging microélectronique joue dans ce cas un rôle principal dans la définition des performances globales du système qui s'étend au-delà de la simple protection de circuits intégrés pour couvrir d'autres fonctions d'intégration de divers dispositifs actifs et passifs. L'axe principal d'étude adopté ici porte sur le packaging d'un module SiP (System-in-Package) intégré en 3D et réalisé en technologie interposer silicium. Le mémoire de thèse s'articule en quatre chapitres : Le premier chapitre donne dans un premier temps une brève introduction aux bandes millimétriques et aux conditions de propagation spécifiques à ces bandes avant de présenter des exemples d'applications relevant de divers domaines civils et militaires. Ensuite, nous dressons un état de l'art des modules SiP millimétriques intégrés selon différentes approches technologiques. Le second chapitre est consacré à l'étude d'un module 60 GHz intégré sur silicium haute-résistivité en technologie interposer silicium. Nous nous intéressons aux méthodes de caractérisation adaptées aux diverses briques technologiques du back-end silicium spécifique aux applications RF-millimétriques et notamment les interconnexions, les matériaux diélectriques ainsi que les antennes intégrées. La caractérisation inclut également un test d'émission-réception entre deux modules 60 GHz. Dans le troisième chapitre, nous proposons d'améliorer le module grâce à un nouveau design d'antennes utilisant le concept de Surface Haute-Impédance (SHI). Ce design est destiné à octroyer plus de compacité et plus de fiabilité au module tout en conservant ses performances électriques. Finalement, le quatrième chapitre détaille les étapes de fabrication du véhicule de test antennaire ainsi que des résultats de caractérisation des antennes et des nouveaux matériaux diélectriques utilisés pour l'empilement technologique. / The evolution of semi-conductor technology nodes has led to a significant miniaturization of today's RF front-ends and to the enhancement of the electrical performance of transceivers at higher frequencies. This leads to the diversification of RF/millimeter-wave (30 – 300 GHz) applications in the fields of telecommunications, multimedia entertainment, automotive and security. More specifically, telecommunications are going through a real revolution with the creation of new standards (such as WiGiG and IEEE 802.11ad) and the introduction of new network architectures based on point-to-point links as the backbone of the 5th generation of mobile networks. In this PhD work, we will focus on integrated wireless and low consumption modules operating in the 57 – 66 GHz band (generally designated as the 60 GHz band). At these frequencies, the free-space wavelength is comparable to the characteristic dimensions of most standard transceiver packages. This opens an opportunity to integrate the antennas as well as other passive components directly to the metal/dielectric stack or in the package. This new generation of electronic devices which are dedicated to the nomad terminal market brings new challenges in terms of electrical performance, mechanical reliability, cost and manufacturability. Microelectronic packaging plays in this case a key role in defining the global performance of the system. Its functions extend beyond the protection of the IC and cover other schemes with opportunities to integrate passive and active devices. This work focuses on the study of an SiP module (System-in-Package) featuring 3D integration on Silicon interposer. The dissertation comprises four chapters and is structured as follows: In the first chapter, a brief introduction of millimeter-waves and their propagation conditions is given. Then, examples of current and emerging civilian and military applications are addressed. State of the art of SiP/mmW modules is then presented according to different technology approaches proposed by industrial and academic contributors. The second chapter is dedicated to the study of a 60 GHz integrated module on a high-resistivity silicon interposer chip. We focus on electrical characterization methods which are adapted to different building blocks of the silicon back-end technology. These include interconnects, dielectrics and integrated antennas. The characterization steps also include full-scale and standard-compliant tests of two communicating 60 GHz modules. In the third chapter, we propose to improve the existing module with a novel antenna design based on a High-Impedance Surface (HIS) reflector. This design is intended to bring more compactness and higher reliability to the original one while conserving the overall electrical performance. Finally, the fourth chapter deals with the fabrications and experimental validation of the antenna test vehicle as well as the wideband characterization of the dielectrics used for the new stack.

abstract: Many communities that once relied on the extractive industries have since turned to tourism to find another source of income. These communities are primarily old mining towns. Since these towns have started to reinvent themselves, they have become important places of study. Previous literature has found specific factors that are common in tourist shopping villages. Currently, there is not much research that has explored the affect the streetscape and servicescape have on visitor experiences. Existing research focuses on urban shopping settings such as shopping malls. This study interviewed employees and surveyed visitors in two suburban tourist shopping villages in Arizona. More specifically, it is aimed to explore how the streetscapes and servicescapes in tourist shopping villages influence visitors' overall experience, intent to return to the village, and their purchasing behavior. This study adds to the current literature on tourist shopping villages and the streetscapes and servicescapes as there is a limited amount of information available. To date, the majority of scholarly information available describes the factors of tourist shopping villages and does not attempt to identify their importance for tourists. This study may serve as a stepping platform for future research. The findings of this study offer important implications for destination marketing organizations, different stakeholders of tourism, and the policy makers. This study primarily focuses on the tourists' view of tourist shopping villages, and can offer insight into how to increase visitor spending. / Dissertation/Thesis / M.S. Community Resources and Development 2013

Les FPGAs (Field Programmable Gate Arrays) sont aujourd'hui des acteurs fondamen-taux dans le domaine des calculateurs qui etait auparavant domin par les microprocesseurs et les ASICs. Le principal enjeu de la conception de FPGA est de trouver le bon compromis entre les performances et la exibilite. Les caractristiques d'un FPGA dependent de trois facteurs : la qualite de l'architecture, la qualite des outils permettant d'implantes l'application sur le FPGA et la technologie utilisee. Le but de cette thse est de proposer une methodologie de conception pour la realisation physique de FPGA en technologie 3 dimensions (3D) ainsi que les outils d'exploration architecturale pour l'empilement en 3D du FPGA arborescent an d'ameliorer lses performances en terme de surface, densite, consommation et vitesse.La premiere partie du manuscrit etudie les dierentes variantes des architectures 2D du FPGA arborescent et l'impact de la migration vers la technologie 3D sur leur topologie. Nous presentons de nombreuses etudes montrant les caracteristiques des reseaux d'interconnexion arborescents, comment ils se comportent en terme de surface et per- formances et comment ils tiennent compte des particularites de l'applicationablee. Mal- heureusement, nous n'avons jamais vu d'avancees en ce qui concerne l'optimisation de telles topologies an d'exploiter leur avantage en terme de surface et consommation, ou encore de resoudre le probleme de longueur des ls qui entrave leurs performances. Tout au long de ce travail, nous avons compris qu'il ne serait pas possible d'optimiser la vitesse sans s'attaquer a la structure m^eme du reseau d'interconnexion arborescent pour l'exploiter a nouveau gr^ace a la technologie 3D. Ce type de technologie peut reduire les problemes de delai du reseau d'interconnexion en orant davantage de exibilite a la conception, au placement et au routage. Un ensemble d'outil d'exploration d'architectures 3D de FPGA a ete developpe pour valider les avancees en terme de performances et surface.La seconde contribution de cette these est le developpement d'une methodologie de conception de circuits FPGA 3D ainsi que l'utilisation des outils de conception classiques (en 2D) pour la realisation physique d'un FPGA arborescent 3D. Tout au long du processus de conception, nous avons ete confrontes aux nombreux problemes que rencontrent les concepteurs 3D en utilisant des outils qui ne sont pas connus pour leurs besoins. De plus, l'utilisation de la technologie 3D risque d'aggraver les performances thermiques. Nous examinons alors precisement l'evolution du comportement thermique lie a l'integration 3D et nous avons montrons comment le contrler en utilisant des techniques de conception tenant compte de la temprature. / Today, FPGAs (Field Programmable Gate Arrays) has become important actors in the computational devices domain that was originally dominated by microprocessors and ASICs. FPGA design big challenge is to nd a good trade-o between exibility and performances. Three factors combine to determine the characteristics of an FPGA: quality of its architecture, quality of the CAD tools used to map circuits into the FPGA, and its electrical technology design. This dissertation aims at exploring a development of Three- dimensional (3D) physical design methodology and exploration tools for 3D Tree-based stacked FPGA architecture to improve area, density, power and performances. The first part of the dissertation is to study the existing variants of 2D Tree-based FPGA architecture and the impact of 3D migration on its topology. We have seen numerous studies showing the characteristics of Tree-based interconnect networks, how they scale in terms of area and performance, and empirically how they relate to particular designs. Nevertheless we never had any breakthrough in optimizing these network topologies to exploit the advantages in area and power consumption and how to deal with the larger wire-length issues that impede performance of Tree-based FPGA architecture. Through the course of the work, we understand that, we would not be able to optimize the speed, unless we break the very backbone of the Tree-based interconnect network and resurrect again by using 3D technology. The 3D-ICs can alleviate interconnect delay issues by ofering exibility in system design, placement and routing. A new set of 3D FPGA architecture exploration tools and technologies developed to validate the advance in performance and area.The second contribution of this thesis is the development 3D physical design methodology and tools using existing 2D CAD tools for the implementation of 3D Tree-based FPGA demonstrator. During the course of design process, we addressed many specic issues that 3D designers will encounter dealing with tools that are not specically designed to meet their needs. In contrast, the thermal performance is expected to worsen with the use of 3D integration. We examined precisely how thermal behavior scales in 3D integration and determine how the temperature can be controlled using thermal design techniques.

Through Silicon Vias (TSVs) are vertical interconnections providing the shortest possible signal paths between vertically stacked chips in 3D packaging. In this thesis, TSVs are fabricated and two novel approaches for the metal filling of TSVs are investigated. A wire bonder is utilized to apply TSV core material in the form of gold stud bumps. The metal filling approaches are carried out by 1) squeezing stud bumps down the TSV holes by utilizing a wafer bonder and 2) stacking stud bumps on the outer periphery of the TSV holes and thereby forcing the material further down. Both approaches have successfully filled TSV holes of varying depths and no voids have been observed. The squeezing approach reaches measured depths of up to 52.9 μm and the stacking approach reaches depths of up to 100 μm.

The 3D integration of dies promises to address the problem of increased die size caused by the slowing of scaling. By partitioning a design among two or more dies and stacking them vertically, the average interconnect length is greatly decreased and thus power is reduced. Also, since smaller dies will have a higher yield, 3D integration will reduce manufacturing costs. However, this increase in yield can only be seen if manufactured dies can be tested before they are stacked. If not, the overall yield for the die stack will be worse than that of the single, larger die. One of the largest issues with prebond die testing is that, to save power, a single die may not have a complete clock distribution network until bonding. This thesis addresses the problem of prebond die testability by ensuring the clock distribution network on a single die will operate with low skew during testing and at a reduced power consumption during operation as compared to a full clock network. The development of a Delay Lock Loop is detailed and used to synchronize disconnected clock networks on a prebond die. This succeeds in providing a test clock network that operates with a skew that is sufficiently close to the target postbond skew. Additionally, a scheme to increase interdie bandwidth by multiplexing Through-Silicon Vias (TSVs) by the system clock is presented. This technique allows for great increase in the number of effective signal TSVs while imposing a negligible area overhead causing no performance degradation.

Os poliomavírus compõem uma grande família de vírus que causam infecções primárias geralmente na infância, e se mantem em condições subclínicas. Em situações de imunossupressão podem causar algumas doenças. Os indivíduos com HIV/AIDS frequentemente apresentam deficiência imunológica e por isso podem exibir maior risco de doenças causadas pelos poliomavírus. A utilização da saliva no diagnóstico e acompanhamento de doenças infecciosas tem sido explorado na literatura. As vantagens de usar a saliva para rastreio se pautam especialmente na coleta não invasiva e segurança no manuseio. O presente estudo teve como objetivo, detectar e quantificar o DNA dos poliomavírus BKV, JCV, de células Merkel e TSV, em fluídos orais (saliva, lavado bucal e fluído gengival crevicular) e comparar com a detecção em soro e urina, meios usualmente utilizados para detecção. Foram coletadas 299 amostras de 42 indivíduos, sendo 22 HIV positivos (GE) e 20 pacientes controle (GC). No GE, 63,6% dos pacientes apresentaram positividade para JCV em pelo menos uma amostra analisada, 54,5% foram positivos para BKV, 18,2% para células Merkel e não houve amostra positiva para TSV. No GC, 45% exibiu positividade para o JCV em pelo menos uma amostra analisada, 80% para BKV e nenhuma participante controle exibiu positividade para células Merkel e TSV. Não houve diferença de frequência de detecção viral entre os grupos estudados em relação às amostras coletadas, ou ainda em relação à idade ou sexo. Entretanto, nas amostras de fluídos orais houve maior prevalência de detecção para o BKV e para células Merkel. Concluímos que fluídos orais, especialmente saliva e lavado bucal, podem ser usados para o rastreamento do BK e JC; e que os indivíduos HIV positivos, sob tratamento antirretroviral não exibem frequências maior de poliomavírus, comparativamente a indivíduos controle. / Polyomavirus is one of the large family of viruses that cause primary infections usually in childhood, and can remain subclinical. In immunosuppression may cause some diseases. Individuals with HIV/AIDS often have immune deficiencies and may be at increased risk for diseases caused by polyomaviruses. The use of saliva in the diagnosis and follow-up of infectious diseases has been explored in the literature. The advantages of using saliva for screening are based on non-invasive collection and handling safety. The aim of present study was to detect and quantify the DNA from BKV, JCV, Merkel cell and TSV polyomaviruses in oral fluids (saliva, mouthwash and gingival crevicular fluid) and to compare it with serum and urine detection, the means usually used for detection. A total of 299 samples were collected from 42 individuals, 22 HIV positive (GE) and 20 control patients (GC). In GE, 63,6% of the patients presented positive for JCV in at least one sample analyzed, 54,5% were positive for BKV, 18,2% for Merkel cell and there was no positive sample for TSV. In GC, 45% showed JCV positivity in at least one analyzed sample, 80% in BKV, and no control participant exhibited positivity for Merkel cell and TSV. There was no difference in the frequency of viral detection among the groups studied in relation to the samples collected, or in relation to age or gender. However, in oral fluid samples there was a higher prevalence of detection for BKV and Merkel cell. We conclude that oral fluids, especially saliva and mouthwash, can be used for the screening of BK e JC; and that HIV positive individuals under antiretroviral treatment do not exhibit higher frequencies of polyomavirus compared to healthy control subjects.

Os poliomavírus compõem uma grande família de vírus que causam infecções primárias geralmente na infância, e se mantem em condições subclínicas. Em situações de imunossupressão podem causar algumas doenças. Os indivíduos com HIV/AIDS frequentemente apresentam deficiência imunológica e por isso podem exibir maior risco de doenças causadas pelos poliomavírus. A utilização da saliva no diagnóstico e acompanhamento de doenças infecciosas tem sido explorado na literatura. As vantagens de usar a saliva para rastreio se pautam especialmente na coleta não invasiva e segurança no manuseio. O presente estudo teve como objetivo, detectar e quantificar o DNA dos poliomavírus BKV, JCV, de células Merkel e TSV, em fluídos orais (saliva, lavado bucal e fluído gengival crevicular) e comparar com a detecção em soro e urina, meios usualmente utilizados para detecção. Foram coletadas 299 amostras de 42 indivíduos, sendo 22 HIV positivos (GE) e 20 pacientes controle (GC). No GE, 63,6% dos pacientes apresentaram positividade para JCV em pelo menos uma amostra analisada, 54,5% foram positivos para BKV, 18,2% para células Merkel e não houve amostra positiva para TSV. No GC, 45% exibiu positividade para o JCV em pelo menos uma amostra analisada, 80% para BKV e nenhuma participante controle exibiu positividade para células Merkel e TSV. Não houve diferença de frequência de detecção viral entre os grupos estudados em relação às amostras coletadas, ou ainda em relação à idade ou sexo. Entretanto, nas amostras de fluídos orais houve maior prevalência de detecção para o BKV e para células Merkel. Concluímos que fluídos orais, especialmente saliva e lavado bucal, podem ser usados para o rastreamento do BK e JC; e que os indivíduos HIV positivos, sob tratamento antirretroviral não exibem frequências maior de poliomavírus, comparativamente a indivíduos controle. / Polyomavirus is one of the large family of viruses that cause primary infections usually in childhood, and can remain subclinical. In immunosuppression may cause some diseases. Individuals with HIV/AIDS often have immune deficiencies and may be at increased risk for diseases caused by polyomaviruses. The use of saliva in the diagnosis and follow-up of infectious diseases has been explored in the literature. The advantages of using saliva for screening are based on non-invasive collection and handling safety. The aim of present study was to detect and quantify the DNA from BKV, JCV, Merkel cell and TSV polyomaviruses in oral fluids (saliva, mouthwash and gingival crevicular fluid) and to compare it with serum and urine detection, the means usually used for detection. A total of 299 samples were collected from 42 individuals, 22 HIV positive (GE) and 20 control patients (GC). In GE, 63,6% of the patients presented positive for JCV in at least one sample analyzed, 54,5% were positive for BKV, 18,2% for Merkel cell and there was no positive sample for TSV. In GC, 45% showed JCV positivity in at least one analyzed sample, 80% in BKV, and no control participant exhibited positivity for Merkel cell and TSV. There was no difference in the frequency of viral detection among the groups studied in relation to the samples collected, or in relation to age or gender. However, in oral fluid samples there was a higher prevalence of detection for BKV and Merkel cell. We conclude that oral fluids, especially saliva and mouthwash, can be used for the screening of BK e JC; and that HIV positive individuals under antiretroviral treatment do not exhibit higher frequencies of polyomavirus compared to healthy control subjects.

Die Arbeit behandelt die zerstörungsfreie Eigenspannungsbestimmung in Silizium von 3D-integrierten Mikrosystemen am Beispiel Wolfram gefüllter TSVs. Dafür wurden die Verfahren der röntgenographischen Spannungsanalyse und der Raman-Spektroskopie genutzt. Interpretiert und verglichen wurden die Ergebnisse mit FE-Simulationen. Als Proben standen Querschliffe eines Doppelchip-Systems zur Verfügung, in denen der obere Chip Wolfram-TSVs enthielt. Beide Chips wurden mit dem Kupfer-Zinn-SLID-Verfahren gebondet. In Experimenten und Simulation konnte der Einfluss von Wolfram-TSVs auf die Netzebenendehnung im Silizium nachgewiesen werden. Die FE-Simulationen zeigen im Silizium Spannungen zwischen -20 und 150 MPa, wenn intrinsische Schichteigenspannungen des Wolframs vernachlässigt werden. Direkt am TSV entwickeln sich Spannungsgradienten von einigen 10 MPa pro Mikrometer. Für die röntgenographische Spannungsanalyse wurden Röntgenbeugungsmessungen am PETRA III-Ring des DESY durchgeführt. Dafür wurde der 2-Theta-Raum in Linienscans untersucht und Beugungsdiagramme aufgenommen. Die ermittelten Dehnungen liegen im Bereich von einigen 10E-5, was uniaxialen Spannungen zwischen 5 und 10MPa entspricht. Im Fall kleiner Gradienten werden die Verläufe der FE-Simulation zufriedenstellend bestätigt. Starke Spannungsgradienten, die sich in wenigen Mikrometern Abstand um das TSV entwickeln, konnten über eine Profilanalyse des Beugungspeaks bestimmt werden. Aus den Ergebnissen lässt sich schließen, dass lateral eng begrenzte Spannungsgradienten von 170 MPa pro µm in TSV-Nähe existieren. Verglichen wurden diese Ergebnisse mit Hilfe der Raman-Spektroskopie. Sowohl die Ergebnisse der Röntgenographischen Spannungsanalyse als auch die der Raman-Spektroskopie lassen darauf schließen, dass die Spannungsgradienten im Silizium in unmittelbarer Nähe zum TSV höher sind als von der FE-Simulation vorhergesagt. Des Weiteren wurde in der Arbeit eine universelle Röntgenbeugung- und Durchstrahlungssimulation XSIM entwickelt, die das Ray-Tracing-Modell nutzt und neben kinematischer und dynamischer Beugung auch optional Rayleigh- und Compton-Streuung berücksichtigt. / This thesis covers the non-destructive determination of residual stress inside Silicon of 3D-integrated micro systems using the example of Tungsten-filled TSVs by X-ray stress analysis and Raman spectroscopy. The results were interpreted and compared by FE-simulations. Double-die systems with Tungsten-TSVs at the top-die were prepared as cross-sections and used as specimens. Both dies were bonded by a Copper-Tin-SLID interconnect. The influence of Tungsten-TSVs on the lattice spacing in Silicon could be demonstrated by experiment as well as in FE-simulations. The FE reveals in Silicon stress between -20 and 150 MPa, if intrinsic stress of deposition inside Tungsten is neglected. The Silicon-Tungsten-interface develops stress gradients of some 10 MPa per micron. The X-ray diffraction measurements for the stress analysis were conducted at the PETRA III-Ring at DESY. The reciprocal 2-Theta-space was investigated by line scans and diffraction patterns were recorded. The registered strain is in the range of some 10E-5, what results in uniaxial stress between 5 and 10 MPa. The strain distributions at line scans of the FE were satisfyingly approved in case of small gradients. Large stress gradients were determined by a profile analysis of the diffraction peak. The investigation shows that stress gradients up to 170 MPa pro micron are present close to the TSV. The results were compared by Raman-spectroscopy. Both X-ray stress analysis and Raman-spectroscopy indicate larger stress gradients nearby the Tungsten-TSV than proposed by the FE-simulation. In addition a universal X-ray diffraction and radiography simulation named XSIM was developed within that thesis. A ray-tracing model was applied to that simulation. XSIM covers both kinematical and dynamical diffraction and optionally allows for Rayleigh and Compton scattering.