Les technologies d'empilement vertical de circuits intégrés, plus connues sous le terme « intégration 3D », ont connu un développement important durant les six dernières années, dans l'optique de proposer une alternative aux approches bidimensionnelles traditionnelles comme les Systems on Chip (SoC). Cette nouvelle architecture a été adaptée au domaine du packaging des circuits intégrés à travers le packaging en 3D réalisé à l'échelle de la plaque ou 3D-WLP pour 3D-Wafer Level Packaging. L'intégration 3D-WLP permet une diminution des tailles des dispositifs finaux, une augmentation de la densité des interconnexions ainsi qu'une réduction des coûts de fabrication. La maîtrise de la réalisation des via traversant, ou TSV pour Through Silicon Via, est une étape clé qui permet d'assurer une connexion électrique entre les différents niveaux empilés. On s'intéresse dans ces travaux de thèse au TSV dans son approche via-last, c'est-à-dire fabriqué en face arrière du dispositif, après les transistors et les niveaux de métallisation de la face avant, et plus particulièrement à l'étape de passivation organique des TSV. En effet, ce via traversant est d'un diamètre trop important pour être complètement rempli avec sa métallisation en cuivre. L'étude concerne donc une solution incluant un remplissage en polymère afin d'améliorer la solution existante en termes de fiabilité et de compatibilité avec des empilements verticaux supplémentaires. / 3D integration technologies for integrated circuits have been widely developed during the six last years in order to propose an alternative to bi-dimensional approaches such as the Systems on Chip (SoC). This new architecture is also used for integrated circuits packaging through 3D-Wafer Level Packaging (3D-WLP). Thus, vertical stacking allows smaller package footprint, higher interconnection density and lower fabrication costs. Through silicon via (TSV) is a key technology that insures vertical electrical interconnection between the stacked levels. This thesis deals with the via-last approach which consists in realizing the TSV at the back-side of the wafer, after the Front End Of the Line (FEOL) and the Back End Of the Line (BEOL), both located at the front-side. During the metallization steps, only a copper liner is electroplated in the TSV since its diameter is too large to achieve a complete metal filling. This study focuses on the TSV polymer insulation step and more specifically, a solution including a TSV polymer filling in order to improve the existing configuration in terms of reliability and compatibility with further 3D stacking.

Three-dimensional integrated circuits (3D ICs) have been designed with the purpose of achieving higher communication speed by reducing the interconnect length between integrated circuits, and integrating heterogeneous functions into one single package, among other advantages. As a growing, new technology, researchers are still studying the different parameters that impact the overall lifetime of such packages in order to ensure the customer receives reliable end products. This study focused on the effect of four design parameters on the lifetime of the interconnects and, in particular, solder balls and through-silicon vias (TSVs). These parameters included TSV pitch, TSV diameter, underfill stiffness and underfill thickness. A three-dimensional finite element model of a 3D IC package was built in ANSYS to analyze the effect of these parameters under thermo-mechanical cyclic loading. The stresses and damage in the interconnects of the IC were evaluated using Coffin-Manson and the energy partitioning fatigue damage models. A three-level Taguchi design of experiment method was utilized to evaluate the effect of each parameter. Minitab software was used to assess the main effects of the selected design parameters. Locations of maximum stresses and possible damage initiation were discussed, and recommendations were made to the manufacturer for package optimization. Due to the very small scale of the interconnects, conducting mechanical tests and measuring strains in small microscopic scale material is very complicated and challenging; therefore, it is very difficult to validate finite element and analytical analysis of stress and strain in microelectronic devices. At the next step of this work, a new device and method were proposed to facilitate testing and strain measurements of material at microscopic scale. This new micro-electromechanical system (MEMS) consisted of two piezoelectric members that were constrained by a rigid frame and that sandwiched the test material. These two piezoelectric members act as load cell and strain measurement sensors. As the voltage is applied to the first member, it induces a force to the specimen and deforms it, which in turn deforms the second piezoelectric member. The second piezoelectric member induces an output voltage that is proportional to its deformation. Therefore, the strain and stresses in the test material can be determined by knowing the mechanical characteristics of the piezoelectric members. Advantages of the proposed system include ease of use, particularly at microscopic scale, adaptability to measure the strain of different materials, and flexibility to measure the modulus of elasticity for an unknown material. An analytical analysis of the device and method was presented, and the finite element simulation of the device was accomplished. The results were compared and discussed. An inelastic specimen was also analyzed and sensitivity of the device to detecting nonlinear behavior was evaluated. A characteristic curve was developed for the specific geometry and piezoelectric material.

Advancements in very large scale integration (VLSI) technology have led to unprecedented transistor and interconnect scaling. Further miniaturization by traditional IC scaling in future planar CMOS technology faces significant challenges. Stacking of ICs (3D IC) using three dimensional (3D) integration technology helps in significantly reducing wiring lengths, interconnect latency and power dissipation while reducing the size of the chip and enhancing performance. Interposer technology with ultra-fine pitch interconnections needs to be developed to support the huge I/O connection requirement for packaging 3D ICs. Through vias in stacked silicon ICs and interposers are the key components of a 3D system. The objective of this dissertation is to model through vias in 3D silicon and glass interposers and, to address power and high-speed signal integrity issues in 3D interposers considering silicon biasing effects. An equivalent circuit model of the through via in silicon interposer (Si TPV) has been proposed considering the bias voltage dependent Metal-Oxide-Semiconductor (MOS) capacitance effect. Important design guidelines and optimizations are proposed for Si TPVs used in the signal delivery network, power delivery network (PDN), and as variable capacitors. Through vias in glass interposers (Glass TPVs) are modeled, designed and simulated by using electromagnetic field solvers. Signal and power integrity analyses are performed for silicon and glass interposers. PDN design is proposed by utilizing the MOS capacitance of the Si TPVs for decoupling.

Clinical signs and lesions of Taura syndrome virus (TSV) infection in Penaeus monodon were investigated by histological and in situ hybridization (ISH) analyses. Mortality among P. monodon inoculated with 2 genotypic variants of TSV (Th04Pm and Th04Lv) appeared on Day 3, with 2 out of 10 shrimp dying. Severe necrosis of cuticular epithelial cells and lymphoid organ spheroids, indicative of acute and chronic phase lesions of TSV infection, respectively, were detected in the samples. Both Th04Pm and Th04Lv belonged to a phylogenetic family of Asian TSV isolates. The results demonstrate that both mortality and histological lesions are associated with TSV infection in P. monodon.Infection with 4 genotypic variants of TSV (Bz01, Th04, UsHi94, and Ve05) in TSV-resistant (TSR) and TSV-susceptible (Kona) Litopenaeus vannamei was investigated. Survival probabilities of TSR shrimp were higher than those for Kona shrimp with all 4 variants. Th04, UsHi94, and Ve05 gave no Taura syndrome lesions with TSR shrimp. In contrast, TSR shrimp challenged with Bz01 and Kona shrimp with all 4 TSV variants exhibited severe necrosis of cuticular epithelial cells and lymphoid organ spheroids. Real-time reverse transcription polymerase chain reaction (RT-PCR) revealed that mean TSV copy numbers in TSR shrimp infected with Bz01, Th04, and UsHi94 were significantly (p < 0.0005) lower than those in Kona shrimp. In contrast, mean TSV copy numbers in TSR and Kona shrimp infected with Ve05 were not significantly different (p > 0.4). The results show that TSR L. vannamei are susceptible to infection but give high survival rates following challenge by all 4 variants of TSV.To identify the viral replication site within shrimp infected cells, the viral RNA was located in association with virus-induced membrane rearrangement by electron microscopic ISH. Ultrastructure in the infected cells, analyzed by transmission electron microscopy, included the induction and proliferation of intracellular vesicle-like membranes, while the intracytoplasmic inclusion bodies and pyknotic nuclei were frequently seen. TSV RNA and TSV particles were found to be associated with the membranous structures. The results suggest that the proliferating membranes carry the RNA replication complex and that they are the site of nascent viral RNA synthesis.

<p>As integrated circuits (ICs) continue to scale to smaller dimensions, long interconnects</p><p>have become the dominant contributor to circuit delay and a significant component of</p><p>power consumption. In order to reduce the length of these interconnects, 3D integration</p><p>and 3D stacked ICs (3D SICs) are active areas of research in both academia and industry.</p><p>3D SICs not only have the potential to reduce average interconnect length and alleviate</p><p>many of the problems caused by long global interconnects, but they can offer greater design</p><p>flexibility over 2D ICs, significant reductions in power consumption and footprint in</p><p>an era of mobile applications, increased on-chip data bandwidth through delay reduction,</p><p>and improved heterogeneous integration.</p><p>Compared to 2D ICs, the manufacture and test of 3D ICs is significantly more complex.</p><p>Through-silicon vias (TSVs), which constitute the dense vertical interconnects in a</p><p>die stack, are a source of additional and unique defects not seen before in ICs. At the same</p><p>time, testing these TSVs, especially before die stacking, is recognized as a major challenge.</p><p>The testing of a 3D stack is constrained by limited test access, test pin availability,</p><p>power, and thermal constraints. Therefore, efficient and optimized test architectures are</p><p>needed to ensure that pre-bond, partial, and complete stack testing are not prohibitively</p><p>expensive.</p><p>Methods of testing TSVs prior to bonding continue to be a difficult problem due to test</p><p>access and testability issues. Although some built-in self-test (BIST) techniques have been</p><p>proposed, these techniques have numerous drawbacks that render them impractical. In this dissertation, a low-cost test architecture is introduced to enable pre-bond TSV test through</p><p>TSV probing. This has the benefit of not needing large analog test components on the die,</p><p>which is a significant drawback of many BIST architectures. Coupled with an optimization</p><p>method described in this dissertation to create parallel test groups for TSVs, test time for</p><p>pre-bond TSV tests can be significantly reduced. The pre-bond probing methodology is</p><p>expanded upon to allow for pre-bond scan test as well, to enable both pre-bond TSV and</p><p>structural test to bring pre-bond known-good-die (KGD) test under a single test paradigm.</p><p>The addition of boundary registers on functional TSV paths required for pre-bond</p><p>probing results in an increase in delay on inter-die functional paths. This cost of test</p><p>architecture insertion can be a significant drawback, especially considering that one benefit</p><p>of 3D integration is that critical paths can be partitioned between dies to reduce their delay.</p><p>This dissertation derives a retiming flow that is used to recover the additional delay added</p><p>to TSV paths by test cell insertion.</p><p>Reducing the cost of test for 3D-SICs is crucial considering that more tests are necessary</p><p>during 3D-SIC manufacturing. To reduce test cost, the test architecture and test</p><p>scheduling for the stack must be optimized to reduce test time across all necessary test</p><p>insertions. This dissertation examines three paradigms for 3D integration - hard dies, firm</p><p>dies, and soft dies, that give varying degrees of control over 2D test architectures on each</p><p>die while optimizing the 3D test architecture. Integer linear programming models are developed</p><p>to provide an optimal 3D test architecture and test schedule for the dies in the 3D</p><p>stack considering any or all post-bond test insertions. Results show that the ILP models</p><p>outperform other optimization methods across a range of 3D benchmark circuits.</p><p>In summary, this dissertation targets testing and design-for-test (DFT) of 3D SICs.</p><p>The proposed techniques enable pre-bond TSV and structural test while maintaining a</p><p>relatively low test cost. Future work will continue to enable testing of 3D SICs to move</p><p>industry closer to realizing the true potential of 3D integration.</p> / Dissertation

Kyoto University (京都大学) / 0048 / 新制・論文博士 / 博士(工学) / 乙第12493号 / 論工博第4047号 / 新制||工||1503(附属図書館) / 28243 / (主査)教授 平尾 一之, 教授 横尾 俊信, 教授 田中 勝久 / 学位規則第4条第2項該当

Les dictats de la course à la miniaturisation et à l'accroissement des performances suivit par les industriels de la microélectronique, se heurte aujourd'hui aux limites physiques, technologiques et économiques. Une alternative innovante pour dépasser ces inconvénients, réside en l'intégration tridimensionnelle de circuits intégrés. Cette technologie consiste à empiler verticalement différents niveaux de circuits aux fonctionnalités diverses. Elle ouvre la voie à des systèmes multifonctions ou hétérogènes, aux performances électriques bien meilleures que les circuits bidimensionnels existants. L'empilement de ces puces est réalisable par l'intermédiaire de vias traversant nommés « Though Silicon Via » (« TSV »), qui sont obtenus par la succession de différentes étapes technologiques, dont une d'entre elles consiste à réaliser par gravure plasma, des microcavités profondes à travers le silicium. Actuellement deux procédés de gravure plasma sont principalement utilisés pour la conception de « TSV », le procédé Bosch et le procédé cryogénique, avec dans les deux cas des avantages et des inconvénients différents. L'objet de cette thèse s'inscrit dans le développement d'un procédé de gravure plasma innovant et alternatif à ceux actuellement utilisés, afin de limiter leurs inconvénients (rugosité de flancs, manque de contrôle des profils, basse température…). Dans cette logique deux procédés de gravure profonde ont été envisagés, exploitant les chimies de gravure SF6/O2/HBr et SF6/O2/HBr/SiF4. L'ensemble de l'étude vise à une meilleure compréhension des mécanismes de gravure et de passivation des cavités à fort facteur de forme grâce en particulier à l'exploitation des techniques d'analyse de surface par XPS. / The dictates of miniaturization and increased performance followed by microelectronics manufacturers faces currently physical, technological and economic limitations. An innovative alternative to these problems is the three-dimensional integration of integrated circuits. This technology involves the vertical stacking of different levels of functionality on the various circuits, and thus opens the way for multifunctional or heterogeneous systems, with electrical performance that are much better than those existing in the two-dimensional circuits. The stacking of these chips is achievable through crossing vias named TSV for "Through Silicon Via", which are obtained by the succession of different technological steps,. One of these steps is the realization by plasma etching of deep silicon microcavities. Currently two plasma etch processes are mainly used for the design of TSV or other silicon structures, the Bosch Process and the Cryogenic process, in both cases with different advantages and disadvantages. The purpose of this thesis is to develop an innovative and alternative plasma etching method comparing to those currently used, to minimize their disadvantages (sidewall roughness, lack of profiles control, low temperature ...). In this logic two deep etch processes have been considered, exploiting SF6/O2/HBr and SF6/O2/HBr/SiF4 etching chemistries. All the studies focuses at better understanding of the mechanisms of etching and passivation of high aspect ratio cavities, especially through exploitation of XPS surface analysis

Avec l’augmentation de la densité de fonctionnalités dans les différents circuits intégrés nous entourant, l’intégration 3D (empilement des puces) devient incontournable. L’un des point-clés d’une telle intégration est la métallisation des vias traversant (TSV, Through Silicon Via) reliant deux puces entre-elles : ces TSV ont des facteurs de forme de plus en plus agressifs, pouvant dépasser 20. Les dépôts des couches barrière à la diffusion du cuivre et d’accroche pour le dépôt électrolytique du cuivre étant actuellement réalisées par dépôt physique en phase vapeur, ceux-ci sont limités en termes de conformité et de facteur de forme. Le travail de cette thèse porte sur le développement du dépôt de couches atomiques (ALD, Atomic Layer Deposition) de cuivre et de nitrure de tantale afin de résoudre les problèmes énoncés lors de la métallisation de TSV. Les précurseurs de cuivre étant actuellement mal connus, différents précurseurs ont été dans un premier temps évalués, afin de sélectionner celui répondant au cahier des charges précis de notre étude. Nous nous sommes par la suite attachés à l’étudier selon deux axes : d’abord en examinant ses propriétés thermodynamiques afin de mieux appréhender les réactions de dépôt, puis lors d’élaboration de films de cuivre sur différents substrats et à différentes conditions afin d’optimiser le procédé d’élaboration de films mince de cuivre. Dans un second temps, nous nous sommes attachés à l’étude d’un précurseur de tantale pour la réalisation de couches barrière à la diffusion. Celui-ci a été étudié en ALD, afin de proposer à l’industrie microélectronique un procédé de dépôt de couches barrière et d’accroche optimisé. Pour finir, nous avons vérifié que l’ALD permet le dépôt conforme dans des TSV à haut facteur de forme, et que les films obtenus ont les propriétés correspondant au cahier des charges de l’industrie la microélectronique. / With the increasing density of features in the various integrated circuits surrounding us, 3D integration (stacking chips) becomes essential. One key point of such integration is the metallization of Through Silicon Vias (TSV) connecting two chips together: the aspect ratio of these TSV will be higher than 20 in the near future. The copper-diffusion barrier layer and seed layer for the electrodeposition of copper are currently deposited by physical vapour deposition, and this technique is limited in terms of conformality in high aspect ratio structure. This work focuses on the development of the Atomic Layer Deposition (ALD) of copper and tantalum nitride in order to propose conformal deposition method of barrier and seed layers. Copper precursors being not well known, different precursors were initially evaluated following the specifications of our study. Once the most promising precursor selected, it has been studied in two different ways. Firstly, a thermodynamic study has been carried out to understand the deposition mechanism; then copper ALD films were deposited on different substrates using different conditions to optimize the deposition. In a second step, a tantalum precursor has been studied for ALD of diffusion barrier, in order to offer the microelectronics industry a deposition method for both barrier and seed layer. Finally, we verified that ALD leads to conformal deposition on high aspect ratio TSV, and that the resulting films have properties corresponding to the specifications of the microelectronic industry.

L'intégration 3D, mode de conception par empilement des puces, vise à la fois la densification des systèmes et la diversification des fonctions. La réduction des dimensions des interconnexions 3D et l'augmentation de la densité de courant accroissent les risques liés à l'électromigration. Une connaissance précise de ce phénomène est requise pour développer un modèle numérique prédictif de la défaillance et ainsi anticiper les difficultés dès le stade de la conception des technologies. Une méthode inédite d'observation in operando dans un MEB de l'endommagement par électromigration des interconnexions 3D est conçue. La structure d'étude avec des vias traversant le silicium (TSV) « haute densité » est testée à 350 °C avec une densité de courant injectée de l'ordre de 1 MA/cm², et simultanément caractérisée. La réalisation régulière de micrographies informe sur la nucléation des cavités, forcée dans la ligne de cuivre au-dessus des TSV, et sur le scénario de leur évolution. La formation d'ilots et la guérison des cavités sont également observées au cours des essais (quelques dizaines à centaines d'heures). Une relation claire est établie entre l'évolution des cavités et celle de la résistance électrique du dispositif. Les différents essais, complétés par des analyses post-mortem (FIB-SEM, EBSD, MET) démontrent l'impact de la microstructure sur le mécanisme de déplétion. Les joints de grains sont des lieux préférentiels de nucléation et influencent l'évolution des cavités. Un effet probable de la taille des grains et de leur orientation cristalline est également révélé. Enfin, l'étude se consacre à l'implémentation d'un modèle multiphysique dans un code éléments finis de la phase de nucléation des cavités. Ce modèle est constitué des principaux termes de gestion de la migration. / 3D integration, conception mode of chips stacking, aims at both systems densification and functions diversification. The downsizing of 3D interconnects dimensions and the increase of current density rise the hazard related to electromigration. An accurate knowledge of the phenomenon is required to develop a predictive modeling of the failure in order to anticipate the difficulties as soon as the stage of technologies conception. Thus, a hitherto unseen SEM in operando observation method is devised. The test structure with “high density” through silicon vias (TSV) is tested at 350 °C with an injected current density of about 1 MA/cm², and simultaneously characterized. Regular shots of micrographs inform about the voids nucleation, forced in copper lines above the TSV, and about the scenario of their evolution. Islets formation and voids curing are also observed during the tens to hundreds hours of tests. A clear relation is established between voids evolution and the one of the electrical resistance. The different tests, completed by post-mortem analyses (FIB-SEM, EBSD, TEM), demonstrate the impact of microstructure on the depletion mechanism. Grains boundaries are preferential voids nucleation sites and influence the voids evolution. A probable effect of grains size and crystallographic orientation is revealed. Finally, the study focuses on the implementation of a multiphysics modeling in a finite elements code of the voids nucleation phase. This modeling is constituted of the main terms of the migration management.

On assiste aujourd’hui à une évolution des systèmes électroniques nomades vers des fonctionnalités plus avancées. Cette complexification des systèmes électroniques nomades nécessite une augmentation de la puissance de calcul des puces électronique, ce qui se peut se traduire par une utilisation d’une technologie CMOS agressive, mais qui se complète aujourd’hui par une technique appelée intégration 3D. Il ne s’agit donc plus d’une évolution classique à l’échelle du transistor suivant la loi de Moore mais à celle de l’échelle plus large du boîtier / système, on parle alors de la loi de « More than Moore ». L’empilement tridimensionnel (3D) des puces électroniques engendre une augmentation de la densité de puissance totale dissipée par unité de surface de l’empilement final. Cette puissance, résultant essentiellement de l’effet joule dans les transistors et l’interconnexion, est une source de chaleur qui contribue à l’augmentation de la température globale de la puce. L’objectif global de cette thèse est d’étudier les échanges thermiques dans un empilement de puces 3D durant leur fonctionnement. On s’attachera à comprendre les effets géométriques ou matériaux de l’empilement ainsi que l’impact du placement des TSV, Bumps ... sur ces échanges thermiques. L’étude s’appuie sur des simulations numériques validées par des mesures expérimentales sur des empilements 3D. Ces études numérique et expérimentale auront comme finalité de déduire des règles de dessin thermiques qui seront validées sur le dessin de circuits basiques ou plus complexes. Dans la suite, ces différents objectifs seront motivés et abordés en détail. L’établissement d’un modèle thermique basé sur des simulations en éléments finis d’un procédé industriel CMOS 65 nm 3D permettra d’aborder le problème de modélisation de la manière la plus précise possible. En effet, les précédentes simulations ont utilisé des modèles compacts – donc de moindre précision que les éléments finis – et un procédé générique qui ne reflète pas toutes les propriétés des matériaux, et en particulier celles des interfaces. Les résultats ainsi obtenus seront validés par des mesures sur des puces empilées réalisées dans le procédé considéré. Dans cette partie expérimentale, l’objectif est de déterminer une cartographie de la température dans un empilement 3D en utilisant des capteurs embarqués dans le silicium, et ce sous différentes conditions d’opération de la puce 3D. Il en ressortira un modèle numérique validé et calibré par des mesures expérimentales. / Today we are witnessing an evolution of mobile electronic systems to more advanced features. The complexity of mobile electronic systems requires an increase in computing power of electronic chips, which can lead to the use of aggressive CMOS technology, but which now completed with a technique called 3D integration. It is more of a classical evolution across the transistor following Moore's law but that of the wider scale of the packaging / system, it is called the law of "More than Moore". Three dimensional (3D) stack of electronic chip generates an increase in the density of total power dissipated per unit area of the final stack. This power, essentially resulting in the Joule effect transistors and interconnection, is a source of heat which contributes to increase the overall temperature of the chip. The global objective of this thesis is to study the heat transfer in a 3D stack of chips during operation. We will seek to understand the geometric or materials effects of the stack and the impact of the placement of TSV, Bumps ... on these heat exchanges. The study is based on numerical simulations validated by experimental measurements on 3D stacks. These numerical and experimental studies have as a goal to deduce thermal design rules that will be validated in the drawing of basic or more complex circuits. In the following, these goals will be motivated and discussed in detail. The establishment of a thermal model based on finite element simulations of an industrial process 3D CMOS 65 nm will address the problem of modelling the most accurate way possible. Indeed, previous simulations used compact models - so that the lower accuracy of finite elements - and a generic method that does not reflect all of the properties of materials, and in particular interfaces. The results obtained will be validated by measurements on stacked chips carried out within the process concerned. In the experimental part, the objective is to determine a thermal mapping in a 3D stack using sensors embedded in the silicon, and under different conditions of 3D chip process. This will provide a numerical model validated and calibrated by experimental measurements.