L'évolution des nœuds technologiques dans l'industrie des semi-conducteurs se traduit de nos jours, dans le domaine des radiofréquences, par une miniaturisation des front-ends et une amélioration des performances électriques des émetteurs-récepteurs à des fréquences de plus en plus hautes. Cette évolution a conduit à la diversification des applications en bandes millimétriques (30 – 300 GHz) dans les secteurs des télécommunications, du divertissement multimédia, de l'automobile et de la sécurité. Plus particulièrement, le secteur des télécommunications connaît aujourd'hui une réelle révolution avec la création de nouveaux standards pour les liens sans-fil millimétriques à courte portée (comme WiGiG et IEEE 802.11ad) et l'apparition de nouvelles architectures basées sur des liaisons point-à-point qui constitueront dans les prochaines années la colonne vertébrale de la cinquième génération des réseaux mobiles. Dans le cadre de ces travaux de thèse, un intérêt particulier sera porté sur les modules intégrés sans fils et à faible consommation opérant dans la bande 57 – 66 GHz (dite généralement 60 GHz). A ces fréquences, la longueur d'onde en espace libre est comparable aux dimensions caractéristiques des boitiers standards utilisés pour l'encapsulation des transceivers. Il devient donc envisageable d'intégrer les antennes ainsi que d'autres composants passifs directement dans l'empilement technologique du circuit ou dans le boitier. Cette nouvelle génération de dispositifs électroniques, destinés au marché des terminaux portables, introduit de nouveaux défis en termes de performances électriques, de fiabilité mécanique, de coût et de possibilités d'industrialisation. Le packaging microélectronique joue dans ce cas un rôle principal dans la définition des performances globales du système qui s'étend au-delà de la simple protection de circuits intégrés pour couvrir d'autres fonctions d'intégration de divers dispositifs actifs et passifs. L'axe principal d'étude adopté ici porte sur le packaging d'un module SiP (System-in-Package) intégré en 3D et réalisé en technologie interposer silicium. Le mémoire de thèse s'articule en quatre chapitres : Le premier chapitre donne dans un premier temps une brève introduction aux bandes millimétriques et aux conditions de propagation spécifiques à ces bandes avant de présenter des exemples d'applications relevant de divers domaines civils et militaires. Ensuite, nous dressons un état de l'art des modules SiP millimétriques intégrés selon différentes approches technologiques. Le second chapitre est consacré à l'étude d'un module 60 GHz intégré sur silicium haute-résistivité en technologie interposer silicium. Nous nous intéressons aux méthodes de caractérisation adaptées aux diverses briques technologiques du back-end silicium spécifique aux applications RF-millimétriques et notamment les interconnexions, les matériaux diélectriques ainsi que les antennes intégrées. La caractérisation inclut également un test d'émission-réception entre deux modules 60 GHz. Dans le troisième chapitre, nous proposons d'améliorer le module grâce à un nouveau design d'antennes utilisant le concept de Surface Haute-Impédance (SHI). Ce design est destiné à octroyer plus de compacité et plus de fiabilité au module tout en conservant ses performances électriques. Finalement, le quatrième chapitre détaille les étapes de fabrication du véhicule de test antennaire ainsi que des résultats de caractérisation des antennes et des nouveaux matériaux diélectriques utilisés pour l'empilement technologique. / The evolution of semi-conductor technology nodes has led to a significant miniaturization of today's RF front-ends and to the enhancement of the electrical performance of transceivers at higher frequencies. This leads to the diversification of RF/millimeter-wave (30 – 300 GHz) applications in the fields of telecommunications, multimedia entertainment, automotive and security. More specifically, telecommunications are going through a real revolution with the creation of new standards (such as WiGiG and IEEE 802.11ad) and the introduction of new network architectures based on point-to-point links as the backbone of the 5th generation of mobile networks. In this PhD work, we will focus on integrated wireless and low consumption modules operating in the 57 – 66 GHz band (generally designated as the 60 GHz band). At these frequencies, the free-space wavelength is comparable to the characteristic dimensions of most standard transceiver packages. This opens an opportunity to integrate the antennas as well as other passive components directly to the metal/dielectric stack or in the package. This new generation of electronic devices which are dedicated to the nomad terminal market brings new challenges in terms of electrical performance, mechanical reliability, cost and manufacturability. Microelectronic packaging plays in this case a key role in defining the global performance of the system. Its functions extend beyond the protection of the IC and cover other schemes with opportunities to integrate passive and active devices. This work focuses on the study of an SiP module (System-in-Package) featuring 3D integration on Silicon interposer. The dissertation comprises four chapters and is structured as follows: In the first chapter, a brief introduction of millimeter-waves and their propagation conditions is given. Then, examples of current and emerging civilian and military applications are addressed. State of the art of SiP/mmW modules is then presented according to different technology approaches proposed by industrial and academic contributors. The second chapter is dedicated to the study of a 60 GHz integrated module on a high-resistivity silicon interposer chip. We focus on electrical characterization methods which are adapted to different building blocks of the silicon back-end technology. These include interconnects, dielectrics and integrated antennas. The characterization steps also include full-scale and standard-compliant tests of two communicating 60 GHz modules. In the third chapter, we propose to improve the existing module with a novel antenna design based on a High-Impedance Surface (HIS) reflector. This design is intended to bring more compactness and higher reliability to the original one while conserving the overall electrical performance. Finally, the fourth chapter deals with the fabrications and experimental validation of the antenna test vehicle as well as the wideband characterization of the dielectrics used for the new stack.

Silicon interposers with TSVs (through-silicon-vias) have been developed in single-crystalline silicon wafer to achieve the high I/O (Input/Output) density. However, single-crystalline silicon interposers suffer a few problems such as cost, electrical performance and reliability. To overcome these shortcomings, an entirely different approach using polycrystalline silicon interposers with thick polymer liners are proposed by Georgia Tech Packaging Research Center, aiming to achieve lower cost silicon interposers with high performance and reliability. The objective of this research is to explore and demonstrate thin polycrystalline silicon as a suitable interposer material to achieve high performance and high reliability TPVs (through-package-vias) in polycrystalline silicon materials with lower cost. Three fundamental challenges were defined, including: 1) low resistivity of the polycrystalline silicon, resulting in high electrical loss; 2) reliability problems resulting from CTE (coefficient of thermal expansion) mismatch between silicon and Cu, and 3) handling and processing of thin silicon panels. A three-dimensional EM (electromagnetic) model was developed to simulate insertion loss and crosstalk of TPVs and compared with TSVs. It has been shown thick polymer liner is effective in addressing the fundamental challenge of low resistivity for the polycrystalline silicon material, leading to better electrical performance of TPVs than TSVs. Parametric studies indicate that thicker sidewall liners result in better electrical performance. A two-dimensional axisymmetric model was established to simulate the first principal stresses in silicon and shear stresses in TPV under thermal cycling. TPVs with thick polymer liners present both smaller principal stresses and shear stresses than TSVs due to the low modulus of polymer. Parametric studies suggest that sidewall liners act as stress buffers and thicker liners result in better mechanical performance. Design guidelines based on simulation results were used in TPV demonstration and test vehicle fabrication. Fracture strength of polycrystalline silicon panel has been fundamentally studied with four-point bending tool and Weibull plot. Surface polymer liners on both sides were introduced to improve the handling of thin silicon panels. Quantitative study showed higher characteristic fracture strength for the panel with surface liners than raw silicon panel. Low cost and double-side processes have been developed for TPV fabrication including UV (ultraviolet) lasers for TPV formation, double laser method for liner fabrication and electroless Cu for seed formation. Key steps and mechanisms for aforementioned processes were summarized and discussed. Polycrystalline silicon interposers with TPVs and up to four metal RDLs (re-distribution layers) were designed, fabricated and characterized. Measurement results showed low insertion loss for both TPVs and CPW (co-planar waveguide) transmission lines. Good model to hardware correlation was also observed. Reliability test vehicles of polycrystalline silicon interposers were also designed and fabricated for thermal cycling test. TPVs survived 4000 cycles without significant resistance changes. SEM imaging on the cross-section of the samples confirmed no Cu or silicon cracking. Magnified images around corner also suggested good adhesion at Cu/liner and silicon/liner interfaces.

Depuis le début du troisième millénaire, des domaines comme l’automobile, le médical, l’industrie agroalimentaire ou l’électronique grand public (smartphone, ordinateur, Hi-fi etc.) sont devenus de plus en plus demandeurs de puces électroniques. Les besoins ont évolué de sorte que la diversification des fonctions des puces électroniques est devenue le nouveau paradigme de la microélectronique. Dans le même temps, des objets biologiques ayant des propriétés très diverses et très spécifiques sont découverts et étudiés. Certains sont conceptuellement considérés comme des solutions ultimes pour répondre à certains défis de l’électronique moderne comme l’utilisation d’origami d’ADN pour la lithographie. De plus il existe une adéquation entre les dimensions des objets biologiques et les transistors les plus fins. Nous nous sommes donc posé la question de savoir si cette convergence d’échelle pouvait permettre la cohabitation de l’électronique et de la biologie pour créer des dispositifs hybrides. Nous avons d’abord étudié l’utilisation d’objets biologiques filiformes comme interconnexions nanométriques. Dans ces recherches des objets biologiques sont utilisés en substitution de matériaux classiques. Toutefois il est loin d’être évident de mesurer leurs propriétés électroniques (mobilité des charges, fiabilité) contrairement aux semi-conducteurs standards. Nous avons donc construit un dispositif de tests électriques facilement utilisable par les biologistes et les électroniciens pour la caractérisation électrique de ces objets biologiques nanométriques. Certains objets biologiques réalisent, de manière naturelle, des interactions ciblées avec des agents biologiques spécifiques parfois pathogènes ou dangereux, ils ont aussi l’avantage de pouvoir être fabriqués à façon comme les protéines. Cela permet d’ouvrir une nouvelle voie dans la fabrication de capteurs dans laquelle les objets biologiques seront interfacés avec les structures électroniques. Nous avons donc travaillé sur la fabrication d'un capteur hybride à base de nanofils de silicium pilotés par un circuit CMOS et permettant un interfaçage entre nanofil et objet biologique. Dans le domaine des capteurs il existe une application qui focalise actuellement beaucoup l’attention, la détection de charges électriques de faibles intensités. Il existe plusieurs techniques mais elles sont toutes perfectibles soit à cause de leur coût soit à cause du temps nécessaire à la réalisation du séquençage soit encore à cause de la difficulté de mise en œuvre du séquençage. Nous avons donc étudié la possibilité de détecter une charge électrique unique. Etant donné la complexité de la question nous avons décidé de répondre à l’aide d’une série de simulations. / Since the beginning of the third millennium, domains such as automotive, medical, food industry or consumer electronics (smartphone, computer, Hi-Fi etc.) are increasingly demanding more electronics chips. Needs have evolved so that, chips have to embed multiple function and diversification has become the new paradigm of electronics researches. At the same time, new biological objects with very specific and diverse properties are discovered and studied. Some are considered as ultimate solution to answer new microelectronics challenges. Moreover, there is a scale similarity between the finest transistors and biological objects. We asked ourselves the question: Can we use this similarity to create hybrid device? First, we investigated the application of nano biological object as interconnections. Despite of research the electrical characterization of biological object is still difficult to manage unlike standard materials as semi-conductors, so we developed an easy to use electrical characterization platform. Some biological object naturally reacts with dangerous or pathogenic agents and could be custom manufactured as proteins. This kind of object can be useful to create new hybrid sensors. We worked on design, manufacturing and characterization of 3D hybrid sensors based on silicon nanowires driven by a CMOS circuit. Then we investigated, with a simulation study, the possibility to detect a fine electric charge with a silicone nanowire which is a current area of interest in sensors research.

A silicon interposer platform with microfluidic cooling is proposed for high-performance computing systems. The key components and technologies for the proposed platform, including electrical and fluidic microbumps, microfluidic vias and heat sinks, and simultaneous flip-chip bonding of the electrical and fluidic microbumps, are developed and demonstrated. Fine-pitch electrical microbumps of 25 µm diameter and 50 µm pitch, fluidic vias of 100 µm diameter, and annular-shaped fluidic microbumps of 150 µm inner diameter and 210 µm outer diameter were fabricated and bonded. Electrical and fluidic tests were conducted to verify the bonding results. Moreover, the thermal and signaling benefits of the proposed platform were evaluated based on thermal measurements and simulations, and signaling simulations. Compared to the conventional air cooling, significant reductions in system temperature and thermal coupling are achieved with the proposed platform. Moreover, the signaling performance is improved due to the reduced temperature, especially for long interconnects on the silicon interposer. A numerical power distribution network (PDN) simulator is developed based on distributed circuit models for on-die power/ground grids, package- and board- level power/ground planes, and the finite difference method. The simulator enables power supply noise simulation, including IR-drop and simultaneous switching noise, for a full chip with multiple blocks of different power, decoupling capacitor, and power/ground pad densities. The distributed circuit model is further extended to include TSVs to enable simulations for 3D PDN. The integration of package- and board- level power/ground planes enables co-simulation of die-package-board PDN and exploration of new PDN configurations.

The goal of the research in this dissertation is to develop techniques for 1) system-on-package integration of passive circuits using ultra-thin advanced polymers called RXP (Rogers experimental polymer), 2) extraction of frequency-dependent material properties up to millimeter-wave frequency, 3) development and synthesis of high-rejection filter topologies, 4) design and characterization of high performance miniaturized embedded passive circuits for microwave and millimeter-wave applications, and 5) development of via and through-silicon via (TSV) enhanced filter design method for integration in high-loss substrate. The RXP material is developed to reduce the layer-count for multi-layer configuration and adoption of advanced fabrication technologies. Frequency-dependent material properties of RXP, ceramic, and other materials have been extracted up to millimeter-wave frequency using parallel-plate resonator method. An automated extraction algorithm has been proposed to handle a large number of frequency samples efficiently. The accuracy of the extraction result has been improved by including the surface roughness effect for conductor operating at high frequency. Using extracted RXP material properties, 2.4/5 GHz WLAN bandpass filters have been designed and characterized. High-rejection bandpass filter topologies for narrow 2.4 GHz and wide 5 GHz have been proposed. The proposed topologies have been synthesized to provide design equations as well as graphical design methodologies using Z-parameters. A new capacitor design called 3D stitched capacitor has been proposed to achieve more symmetric layout by providing balanced shunt parasitics. The proposed topologies and design methodologies have been verified through the measurement of high-rejection RXP bandpass filters. Good correlation between the simulation and measurement was observed demonstrating an effective design methodology and embedding bandpass filters with good performance. Dual-band bandpass filters for WLAN applications have been implemented and measured. Instead of connecting two bandpass filter circuits, a new single bandpass filter topology has been developed with a compact size as well as high isolation between passbands. High-rejection duplexer has been designed in RXP substrate for chip-last embedded IC technology, and a novel matching circuit has been applied for the miniaturization as well. The 60 GHz V-band has special interest for wireless applications because of its high attenuation characteristics because of atmospheric oxygen. Millimeter-wave passive circuits such as bandpass filter, dual-band filter, and duplexer have been designed, and self-resonant frequency of passive components has been carefully avoided using the proposed method. For low-cost system integration, silicon interposer with through-silicon-via (TSV) technology has been studied. The filter design method for high-loss substrate has been proposed. The coupling characteristic of TSV has been investigated for obtaining good insertion loss in lossy substrates such as silicon, and TSV characteristics has been used to design bandpass and highpass filters. To demonstration of concept, bandpass filters with good insertion loss have been realized on high-loss FR4 substrate.

In this research, wafer-level flexible input/output interconnection technologies, Mechanically Flexible Interconnects (MFIs), have been developed. First, Au-NiW MFIs with 65 µm vertical elastic range of motion are designed and fabricated. The gold passivation layer is experimentally verified to not only lower the electrical resistance but also significantly extend the life-time of the MFIs. In addition, a photoresist spray-coating based fabrication process is developed to scale the in-line pitch of MFIs from 150 µm to 50 µm. By adding a contact-tip, Au-NiW MFI could realize a rematable assembly on a substrate with uniform pads and a robust assembly on a substrate with 45 µm surface variation. Last but not least, multi-pitch multi-height MFIs (MPMH MFIs) are formed using double-lithography and double-reflow processes, which can realize an MFI array containing MFIs with various heights and various pitches. Using these advanced MFIs, large scale heterogeneous systems which can provide high performance system-level interconnections are demonstrated. For example, the demonstrated 3D interposer stacking enabled by MPMH MFIs is promising to realize a low profile and cavity-free robust stacking system. Moreover, bridged multiinterposer system is developed to address the reticle and yield limitations of realizing a large scale system using current 2.5D integration technologies. The high-bandwidth interconnection available within interposer can be extended by using a silicon chip to bridge adjacent interposers. MFIs assisted thermal isolation is also developed to alleviate thermal coupling in a high-performance 3D stacking system.

here is an increasing demand for higher bandwidth (BW) between logic and memory ICs for future smart mobile systems. Such high BW are proposed to be achieved using 3D interposers that have ultra-small through-package-via (TPVs) interconnections to connect the logic device on one side of the interposer to the memory on the other side. The current approach is primarily based on organic or silicon interposers. However, organic interposers face several challenges due to their poor dimensional stability, and coefficient of thermal expansion (CTE) mismatch to silicon ICs. Silicon interposers made with back-end-of-line (BEOL) wafer processes can achieve the required wiring and I/O density, but are not cost effective, and in addition exhibit higher electrical loss due to the semiconducting nature of the Si substrate. In this research, ultra-thin 3D Glass Interposers are studied as a superior alternative to organic and silicon interposers. The fundamental focus of this research is to achieve ultra-small TPVs in thin glass with dimensions similar to that of through-silicon-vias (TSVs) in silicon. The objective of this research is to study and demonstrate ultra-small pitch (30µm) TPV hole formation (10µm diameter), metallization and electrical characterization in ultra-thin (30µm) glass substrates. To meet these objectives, this study focusses on four main research tasks: a) electrical modeling and design of ultra-small TPVs in glass, b) small diameter TPV hole formation with minimum defects, c) copper metallization of TPVs with reliable adhesion, and d) electrical characterization of TPVs. This research reports the first demonstration of ultra-small TPVs (10-15µm in diameter) in ultra-thin glass interposer substrates (30µm). A thin-glass handling method is developed using polymer surface layers to achieve defect-free handling of glass even at thicknesses as low as 30µm. Several TPV formation methods are explored including excimer laser ablation using 193nm (ArF) lasers to form TPVs with smallest diameter and pitch. A brief study on the through-put capabilities of these excimer lasers is also discussed. The fundamental approach to TPV metallization involves a semi-additive-plating process (SAP) using electroless and electrolytic copper deposition techniques. The resulting side-wall surfaces of TPVs after metallization are analyzed through SEM imaging of TPV cross-sections, and are further characterized using nano-indentation tests. Additionally, thermo-mechanical reliability tests and failure analysis are performed to study the reliability of TPVs that are metallized with Cu. This research culminates in design, fabrication and electrical characterization of small pitch TPVs in ultra-thin glass interposers (30µm).

La densité des circuits intégrés n’a pas cessé d’augmenter depuis la découverte du transistor en 1947, à travers la réduction de la taille de leurs composants. Cependant, cette miniaturisation se heurte aujourd’hui à certaines barrières et la réduction de la longueur de grille des transistors ne permet plus à elle seule l’augmentation des performances globales des circuits intégrés. L’industrie de la microélectronique s’est donc tournée vers de nouvelles solutions d’intégrations hétérogènes visant à développer la diversification des fonctionnalités proposées par les circuits. Parmi ces solutions, l’intégration 3D consistant à empiler plusieurs puces de silicium les unes sur les autres à l’aide de « Through Silicon Vias » (TSV) apparait très prometteuse. Toutefois, de telles structures mettront du temps à atteindre leur maturité puisqu’elles requièrent l’évolution de tout l’écosystème industriel. Une solution intermédiaire en termes de maturité technologique réside dans l’utilisation de l’interposeur : un substrat aminci placé entre les puces haute densité et le « Ball Grid Array » faisant office de plateforme d’intégration permettant le placement côte à côte de puces hétérogènes ainsi que la réalisation d’une forte densité d’interconnexions. Cependant, l’ajout de l’interposeur dans le système a pour effet l’augmentation de l’impédance du réseau de distribution de puissance. L’intégration d’une capacité de découplage au sein de l’interposeur répond à cette problématique en assurant l’intégrité de l’alimentation dans des structures tridimensionnelles.L’objectif de cette thèse de doctorat consiste en l’étude de l’intégration d’un nouveau type de capacité intégrée au sein de l’interposeur silicium. Cette capacité basée sur un empilement Métal-Isolant-Métal (MIM) tridimensionnelle a pour particularité de traverser l’intégralité de l’épaisseur de l’interposeur et d’être co-intégrée avec les TSV.La première étape de l’étude de ce nouveau composant intégré a été la définition d’une architecture performante, réalisée à travers une étude de modélisation permettant l’évaluation de l’influence des nombreux paramètres géométriques et matériaux entrant en jeu. Cette étude a permis de mettre en avant les faibles valeurs d’ESR et d’ESL atteignable par la structure (de l’ordre du m et fH respectivement). Ensuite, la réalisation de la capacité a nécessité le développement de procédés de fabrication innovants permettant le dépôt d’un empilement MIM dans des matrices de vias profonds ainsi que sa co-intégration avec les TSV. Enfin, les performances du composant ont été évaluées à travers la réalisation et la caractérisation d’un démonstrateur de test ainsi qu’une campagne de simulations électromagnétiques par éléments finis. Une densité de capacité de 20 nF.mm-2 a été atteinte sur ce démonstrateur, offrant un gain d’un facteur supérieur à 6 par rapport à une structure planaire. / Integrated circuits density never stopped rising since the discovery of the transistor in 1947, through components size shrinking. However, this miniaturization now encounters barriers and reduction of transistor’s gate size alone no longer allows integrated circuits overall performances increase. Therefore, microelectronic industry turned to new heterogeneous integration solutions aiming to develop the diversification of functionalities offered by the circuits. Among these solutions, 3D integration involving stacking several silicon dies on top of each other with the help of Through Silicon Vias (TSV) appears to be promising. Nevertheless, such structures will take times to reach maturity since they require the evolution of the whole industrial ecosystem. A transitional solution in term of technological maturity lies in the use of the interposer: a thinned substrate placed between the high density silicon dies and the Ball Grid Array acting as an integration platform allowing side by side placement of heterogeneous dies as well as high density interconnections. However, the addition of the interposer in the system leads to the increase of the Power Delivery Network impedance. The integration of a decoupling capacitor on the interposer resolves this issue by ensuring power integrity within 3D structures.The objective of this PhD thesis consists in the study of different aspects of a new kind of integrated capacitor within the silicon interposer. This 3D Metal-Insulator-Metal (MIM) capacitor has the particularity to cross over the whole silicon interposer’s thickness and to be co-integrated with TSV.The first step of this new integrated component study has been the definition of an efficient architecture, achieved through a modeling study allowing the influence evaluation of the numerous geometrical and material parameters coming into play. This modeling study pointed out the low ESR and ESL values achievable by the structure (in the m and fH range respectively). Then, the fabrication of the capacitor required the development of innovative process steps allowing the deposition of a MIM stack in deep vias matrices as well as co-integration with TSV. Finally, component performances have been evaluated through the fabrication of a test demonstrator as well as a finites elements electromagnetic simulation campaign. A capacitance density of 20 nF.mm-2 has been reached on this demonstrator, showing an increase up to a factor 6 compared to a planar structure.

No description available.

Current trends in electronic industry, such as Internet of Things (IoT) and Cloud Computing call for high interconnect bandwidth, increased number of active devices and high IO count. Hence the integration of on silicon optical waveguides becomes an alternative approach to cope with the performance demands. The application and fabrication of horizontal (planar) and vertical (Through Silicon Vias - TSVs) optical waveguides are discussed here. Coupling elements are used to connect both waveguide structures. Two micro-structuring technologies for integration of coupling elements are investigated: μ-mirror fabrication by nanoimprint (i) and dicing technique (ii). Nanoimprint technology creates highly precise horizontal waveguides with polymer (refractive index nC = 1.56 at 650 nm) as core. The waveguide ends in reflecting facets aligned to the optical TSVs. To achieve Total Internal Reflection (TIR), SiO2 (nCl = 1.46) is used as cladding. TSVs (diameter 20-40μm in 200-380μm interposer) are realized by BOSCH process1, oxidation and SU-8 filling techniques. To carry out the imprint, first a silicon structure is etched using a special plasma etching process. A polymer stamp is then created from the silicon template. Using this polymer stamp, SU-8 is imprinted aligned to vertical TSVs over Si surface.Waveguide dicing is presented as a second technology to create coupling elements on polymer waveguides. The reflecting mirror is created by 45° V-shaped dicing blade. The goal of this work is to develop coupling elements to aid 3D optical interconnect network on silicon interposer, to facilitate the realization of the emerging technologies for the upcoming years.