Silicon interposers with TSVs (through-silicon-vias) have been developed in single-crystalline silicon wafer to achieve the high I/O (Input/Output) density. However, single-crystalline silicon interposers suffer a few problems such as cost, electrical performance and reliability. To overcome these shortcomings, an entirely different approach using polycrystalline silicon interposers with thick polymer liners are proposed by Georgia Tech Packaging Research Center, aiming to achieve lower cost silicon interposers with high performance and reliability. The objective of this research is to explore and demonstrate thin polycrystalline silicon as a suitable interposer material to achieve high performance and high reliability TPVs (through-package-vias) in polycrystalline silicon materials with lower cost. Three fundamental challenges were defined, including: 1) low resistivity of the polycrystalline silicon, resulting in high electrical loss; 2) reliability problems resulting from CTE (coefficient of thermal expansion) mismatch between silicon and Cu, and 3) handling and processing of thin silicon panels. A three-dimensional EM (electromagnetic) model was developed to simulate insertion loss and crosstalk of TPVs and compared with TSVs. It has been shown thick polymer liner is effective in addressing the fundamental challenge of low resistivity for the polycrystalline silicon material, leading to better electrical performance of TPVs than TSVs. Parametric studies indicate that thicker sidewall liners result in better electrical performance. A two-dimensional axisymmetric model was established to simulate the first principal stresses in silicon and shear stresses in TPV under thermal cycling. TPVs with thick polymer liners present both smaller principal stresses and shear stresses than TSVs due to the low modulus of polymer. Parametric studies suggest that sidewall liners act as stress buffers and thicker liners result in better mechanical performance. Design guidelines based on simulation results were used in TPV demonstration and test vehicle fabrication. Fracture strength of polycrystalline silicon panel has been fundamentally studied with four-point bending tool and Weibull plot. Surface polymer liners on both sides were introduced to improve the handling of thin silicon panels. Quantitative study showed higher characteristic fracture strength for the panel with surface liners than raw silicon panel. Low cost and double-side processes have been developed for TPV fabrication including UV (ultraviolet) lasers for TPV formation, double laser method for liner fabrication and electroless Cu for seed formation. Key steps and mechanisms for aforementioned processes were summarized and discussed. Polycrystalline silicon interposers with TPVs and up to four metal RDLs (re-distribution layers) were designed, fabricated and characterized. Measurement results showed low insertion loss for both TPVs and CPW (co-planar waveguide) transmission lines. Good model to hardware correlation was also observed. Reliability test vehicles of polycrystalline silicon interposers were also designed and fabricated for thermal cycling test. TPVs survived 4000 cycles without significant resistance changes. SEM imaging on the cross-section of the samples confirmed no Cu or silicon cracking. Magnified images around corner also suggested good adhesion at Cu/liner and silicon/liner interfaces.

A silicon interposer platform with microfluidic cooling is proposed for high-performance computing systems. The key components and technologies for the proposed platform, including electrical and fluidic microbumps, microfluidic vias and heat sinks, and simultaneous flip-chip bonding of the electrical and fluidic microbumps, are developed and demonstrated. Fine-pitch electrical microbumps of 25 µm diameter and 50 µm pitch, fluidic vias of 100 µm diameter, and annular-shaped fluidic microbumps of 150 µm inner diameter and 210 µm outer diameter were fabricated and bonded. Electrical and fluidic tests were conducted to verify the bonding results. Moreover, the thermal and signaling benefits of the proposed platform were evaluated based on thermal measurements and simulations, and signaling simulations. Compared to the conventional air cooling, significant reductions in system temperature and thermal coupling are achieved with the proposed platform. Moreover, the signaling performance is improved due to the reduced temperature, especially for long interconnects on the silicon interposer. A numerical power distribution network (PDN) simulator is developed based on distributed circuit models for on-die power/ground grids, package- and board- level power/ground planes, and the finite difference method. The simulator enables power supply noise simulation, including IR-drop and simultaneous switching noise, for a full chip with multiple blocks of different power, decoupling capacitor, and power/ground pad densities. The distributed circuit model is further extended to include TSVs to enable simulations for 3D PDN. The integration of package- and board- level power/ground planes enables co-simulation of die-package-board PDN and exploration of new PDN configurations.

The goal of the research in this dissertation is to develop techniques for 1) system-on-package integration of passive circuits using ultra-thin advanced polymers called RXP (Rogers experimental polymer), 2) extraction of frequency-dependent material properties up to millimeter-wave frequency, 3) development and synthesis of high-rejection filter topologies, 4) design and characterization of high performance miniaturized embedded passive circuits for microwave and millimeter-wave applications, and 5) development of via and through-silicon via (TSV) enhanced filter design method for integration in high-loss substrate. The RXP material is developed to reduce the layer-count for multi-layer configuration and adoption of advanced fabrication technologies. Frequency-dependent material properties of RXP, ceramic, and other materials have been extracted up to millimeter-wave frequency using parallel-plate resonator method. An automated extraction algorithm has been proposed to handle a large number of frequency samples efficiently. The accuracy of the extraction result has been improved by including the surface roughness effect for conductor operating at high frequency. Using extracted RXP material properties, 2.4/5 GHz WLAN bandpass filters have been designed and characterized. High-rejection bandpass filter topologies for narrow 2.4 GHz and wide 5 GHz have been proposed. The proposed topologies have been synthesized to provide design equations as well as graphical design methodologies using Z-parameters. A new capacitor design called 3D stitched capacitor has been proposed to achieve more symmetric layout by providing balanced shunt parasitics. The proposed topologies and design methodologies have been verified through the measurement of high-rejection RXP bandpass filters. Good correlation between the simulation and measurement was observed demonstrating an effective design methodology and embedding bandpass filters with good performance. Dual-band bandpass filters for WLAN applications have been implemented and measured. Instead of connecting two bandpass filter circuits, a new single bandpass filter topology has been developed with a compact size as well as high isolation between passbands. High-rejection duplexer has been designed in RXP substrate for chip-last embedded IC technology, and a novel matching circuit has been applied for the miniaturization as well. The 60 GHz V-band has special interest for wireless applications because of its high attenuation characteristics because of atmospheric oxygen. Millimeter-wave passive circuits such as bandpass filter, dual-band filter, and duplexer have been designed, and self-resonant frequency of passive components has been carefully avoided using the proposed method. For low-cost system integration, silicon interposer with through-silicon-via (TSV) technology has been studied. The filter design method for high-loss substrate has been proposed. The coupling characteristic of TSV has been investigated for obtaining good insertion loss in lossy substrates such as silicon, and TSV characteristics has been used to design bandpass and highpass filters. To demonstration of concept, bandpass filters with good insertion loss have been realized on high-loss FR4 substrate.

La densité des circuits intégrés n’a pas cessé d’augmenter depuis la découverte du transistor en 1947, à travers la réduction de la taille de leurs composants. Cependant, cette miniaturisation se heurte aujourd’hui à certaines barrières et la réduction de la longueur de grille des transistors ne permet plus à elle seule l’augmentation des performances globales des circuits intégrés. L’industrie de la microélectronique s’est donc tournée vers de nouvelles solutions d’intégrations hétérogènes visant à développer la diversification des fonctionnalités proposées par les circuits. Parmi ces solutions, l’intégration 3D consistant à empiler plusieurs puces de silicium les unes sur les autres à l’aide de « Through Silicon Vias » (TSV) apparait très prometteuse. Toutefois, de telles structures mettront du temps à atteindre leur maturité puisqu’elles requièrent l’évolution de tout l’écosystème industriel. Une solution intermédiaire en termes de maturité technologique réside dans l’utilisation de l’interposeur : un substrat aminci placé entre les puces haute densité et le « Ball Grid Array » faisant office de plateforme d’intégration permettant le placement côte à côte de puces hétérogènes ainsi que la réalisation d’une forte densité d’interconnexions. Cependant, l’ajout de l’interposeur dans le système a pour effet l’augmentation de l’impédance du réseau de distribution de puissance. L’intégration d’une capacité de découplage au sein de l’interposeur répond à cette problématique en assurant l’intégrité de l’alimentation dans des structures tridimensionnelles.L’objectif de cette thèse de doctorat consiste en l’étude de l’intégration d’un nouveau type de capacité intégrée au sein de l’interposeur silicium. Cette capacité basée sur un empilement Métal-Isolant-Métal (MIM) tridimensionnelle a pour particularité de traverser l’intégralité de l’épaisseur de l’interposeur et d’être co-intégrée avec les TSV.La première étape de l’étude de ce nouveau composant intégré a été la définition d’une architecture performante, réalisée à travers une étude de modélisation permettant l’évaluation de l’influence des nombreux paramètres géométriques et matériaux entrant en jeu. Cette étude a permis de mettre en avant les faibles valeurs d’ESR et d’ESL atteignable par la structure (de l’ordre du m et fH respectivement). Ensuite, la réalisation de la capacité a nécessité le développement de procédés de fabrication innovants permettant le dépôt d’un empilement MIM dans des matrices de vias profonds ainsi que sa co-intégration avec les TSV. Enfin, les performances du composant ont été évaluées à travers la réalisation et la caractérisation d’un démonstrateur de test ainsi qu’une campagne de simulations électromagnétiques par éléments finis. Une densité de capacité de 20 nF.mm-2 a été atteinte sur ce démonstrateur, offrant un gain d’un facteur supérieur à 6 par rapport à une structure planaire. / Integrated circuits density never stopped rising since the discovery of the transistor in 1947, through components size shrinking. However, this miniaturization now encounters barriers and reduction of transistor’s gate size alone no longer allows integrated circuits overall performances increase. Therefore, microelectronic industry turned to new heterogeneous integration solutions aiming to develop the diversification of functionalities offered by the circuits. Among these solutions, 3D integration involving stacking several silicon dies on top of each other with the help of Through Silicon Vias (TSV) appears to be promising. Nevertheless, such structures will take times to reach maturity since they require the evolution of the whole industrial ecosystem. A transitional solution in term of technological maturity lies in the use of the interposer: a thinned substrate placed between the high density silicon dies and the Ball Grid Array acting as an integration platform allowing side by side placement of heterogeneous dies as well as high density interconnections. However, the addition of the interposer in the system leads to the increase of the Power Delivery Network impedance. The integration of a decoupling capacitor on the interposer resolves this issue by ensuring power integrity within 3D structures.The objective of this PhD thesis consists in the study of different aspects of a new kind of integrated capacitor within the silicon interposer. This 3D Metal-Insulator-Metal (MIM) capacitor has the particularity to cross over the whole silicon interposer’s thickness and to be co-integrated with TSV.The first step of this new integrated component study has been the definition of an efficient architecture, achieved through a modeling study allowing the influence evaluation of the numerous geometrical and material parameters coming into play. This modeling study pointed out the low ESR and ESL values achievable by the structure (in the m and fH range respectively). Then, the fabrication of the capacitor required the development of innovative process steps allowing the deposition of a MIM stack in deep vias matrices as well as co-integration with TSV. Finally, component performances have been evaluated through the fabrication of a test demonstrator as well as a finites elements electromagnetic simulation campaign. A capacitance density of 20 nF.mm-2 has been reached on this demonstrator, showing an increase up to a factor 6 compared to a planar structure.

Three-dimensional (3-D) system integration is believed to be a promising technology and has gained tremendous momentum in the semiconductor industry recently. The Silicon interposer is the key enabler for the 3-D systems, and is expected to have high input/output counts, fine wiring lines and many TSVs. Modeling and design of the silicon interposer can be challenging and is becoming a critical task. This dissertation mainly focuses on developing an efficient modeling approach for silicon interposers in 3-D systems. The developed numerical methods can be classified as several categories. 1. The investigation of the coupling effects in large TSV arrays in silicon interposers. The importance of coupling between TSVs for low resistivity silicon substrates is quantified both in frequency and time domains. This has been compared with high resistivity silicon substrates. 2. The development of an electromagnetic modeling approach for non-uniform TSVs. To model the complex TSV structures, an approach for modeling conical TSVs is proposed first. Later a hybrid modeling method which combines the conical TSV modeling method and cylindrical modeling method is proposed to model the non-uniform TSV structures. 3. The development of a hybrid modeling approach for power delivery networks (PDN) with through-silicon vias (TSVs). The proposed approach extends multi-layer finite difference method (M-FDM) to include TSVs by extracting their parasitic behavior using an integral equation based solver. 4. The development of an efficient approach for modeling signal paths with TSVs in silicon interposers. The proposed method utilizes the 3-D finite-difference frequency-domain (FDFD) method to model the redistribution layer (RDL) transmission lines. A new formulation on incorporating multiport networks into the 3-D FDFD formulation is presented to include the parasitic effects of TSV arrays in the system matrix. 5. The development of a 3-D FDFD non-conformal domain decomposition method. The proposed method allows modeling individual domains independently using the FDFD method with non-matching meshing grids at interfaces. This non-conformal domain decomposition method is applied to model interconnections in silicon interposer.

Novel polymer-enhanced photodefined through-silicon via (TSV) and passive technologies have been demonstrated for silicon interposers to obtain compact heterogeneous computing and mixed-signal systems. These technologies include: (1) Polymer-clad TSVs with thick (~20 µm) liners to help reduce TSV losses and stress, and obtain optical TSVs in parallel for interposer-to-interposer long-distance communication; (2) Polymer-embedded vias with copper vias embedded in polymer wells to significantly reduce the TSV losses; (3) Coaxial vias in polymer wells to reduce the TSV losses with controlled impedance; (4) Antennas over polymer wells to attain a high radiation efficiency; and (5) High-Q inductors over polymer wells. Cleanroom fabrication and characterization of the technologies have been demonstrated. For the fabricated polymer-clad TSVs, resistance and synchrotron x-ray diffraction (XRD) measurements have been demonstrated. High-frequency measurements up to 170 GHz and time-domain measurements up to 10 Gbps have been demonstrated for the fabricated polymer-embedded vias. For the fabricated coaxial vias and inductors, high-frequency measurements up to 50 GHz have been demonstrated. Lastly, for the fabricated antennas, measurements in the W-band have been demonstrated.