As nanometer Very Large Scale Integration (VLSI) demands more transistor density to fabricate multi-cores and memory blocks in a limited die size, many researches have been performed to keep Moore's Low in two different ways: 2D geometric shrinking and 3D vertical wafer stacking. For the geometric shrinking, nano patterning with 193nm lithography equipment is one of the most fundamental challenges beyond 22nm while the next-generation lithography, such as Extreme Ultra-Violet (EUV) lithography still faces tremendous challenges for volume production in the near future. As a practical solution, Double Patterning Lithography (DPL) has become a leading candidate for sub-20nm lithography process. Another approach for multi-core integration is 3D wafer stacking with Through Silicon Via (TSV). Computer-Aided-Design (CAD) approaches to enable robust DPL and TSV technology are the main focus of this dissertation. DPL poses new challenges for overlay and layout decomposition. Therefore, overlay induced variation modeling and efficient decomposition for better manufacturability are in great demand. Since the variation of metal space caused by overlay results in coupling capacitance variation, we first model metal spacing variation with individual overlay sources. Then, all overlay sources are considered to determine the worst timing with coupling capacitance variation. Non-parallel pattern caused by overlay is converted to parallel one with equivalent spacing having the same delay to be applicable of a traditional RC extraction flow. Our experiments show that the delay variation due to overlay in DPL can be up to 9.1%, and well decomposed layout can reduce the variability. For DPL layout decomposition, we propose a multi-objective and flexible framework for stitch minimization, balanced density, and overlay compensation, simultaneously. We use a graph theoretic algorithm for minimum stitch insertion and balanced density. Additional decomposition constraints for overlay compensation are obtained by Integer Linear Programming (ILP). Robust contact decomposition can be obtained with additional constraints. With these constraints, global decomposition is performed using a modified Fiduccia-Mattheyses (FM) graph partitioning algorithm. Experimental results show that the proposed framework is highly scalable and fast: we can decompose all 15 benchmark circuits in five minutes in a density balanced fashion, while an ILP-based approach can finish only the smallest five circuits. In addition, we can remove more than 95% of the timing variation induced by overlay for tested structures. Three-dimensional integration has new manufacturing and design challenges such as device variation due to TSV induced stress and timing corner mismatch between different stacked dies. Since TSV fill material and silicon have different Coefficients of Thermal Expansion (CTE), TSV causes silicon deformation due to different temperatures at chip manufacturing and operating. Therefore, the systematic variation due to TSV induced stress should be considered for robust 3D IC design. We propose systematic TSV stress aware timing analysis and show how to optimize layout for better performance. First, a stress contour map with an analytical radial stress model is generated. Then, the tensile stress is converted to hole and electron mobility variations depending on geometric relations between TSVs and transistors. Mobility variation aware cell library and netlist are generated and incorporated in an industrial timing engine for 3D-IC timing analysis. TSV stress induced timing variations can be as much as 10% for an individual cell. As an application for layout optimization, we can exploit the stress-induced mobility enhancement to improve timing on critical cells. We show that stress-aware perturbation could reduce cell delay by up to 14.0% and critical path delay by 6.5% in our test case. Three-dimensional Clock Tree Synthesis (3D CTS) is one of the main design difficulties in 3D integration because clock network is spreading over all tiers. In 3D CTS, timing corner mismatch between tiers is caused because each tier is manufactured in independent process. Therefore, inter-die variation should be considered to analyze and optimize for paths spreading over several tiers in 3D CTS. In addition, mobility variation of a clock buffer due to stress from TSV can cause unexpected skew which degrades overall chip performance. Therefore, we propose clock period optimization to consider both timing corner mismatch and TSV induced stress. In our experiments, we show that our clock buffer tier assignment reduces clock period variation up to 34.2%, and the most of stress-induced skew can be removed by our stress-aware CTS. Overall, we show that performance gain can be up to 5.7% with the proposed CTS algorithm. As technology scaling continues toward 14nm and 3D-integration, this dissertation addresses several key issues in the design-manufacturing interface, and proposes unified analysis and optimization techniques for effective design and manufacturing integration. / text

The aggressive scaling of the semiconductor technology following the Moore’s Law has delivered true system-on-chip (SoC) integration. Network-on-chip (NoC) has been recently introduced as an effective solution for scalable on-chip communication since dedicated point-to-point (P2P) interconnection and shared bus architecture become performance and power bottlenecks in the SoCs. This dissertation studies three critical NoC challenges such as latency, power, and compatibility with emerging technologies in aspect of an architecture and physical design level. Latency is a key issue in NoC since the performance of applications considerably depends on resource sharing policies employed in an on-chip network. NoCs have been mainly developed to improve network-level performance that captures the inherent performance characteristics of a network itself, but the network-level optimizations are not directly related to application- or system-level performance. In addition, memory latency on NoC critically affects the performance of applications or systems. We propose a synchronous dynamic random access memory (SDRAM) aware NoC design to optimize memory throughput, latency, and design complexity. Furthermore, it is extended to an application-aware NoC design to provide the quality-of-service (QoS) of memory for various applications. NoC provides great on-chip communication. However, it brings no true relief to power budget when the on-chip network scales in terms of complexity/size and signal bandwidth. The combination of NoC and other techniques has the potential to reduce power. We study two power saving research topics for NoC: (a) we propose a voltage-frequency island (VFI) aware NoC optimization framework with a better tradeoff between power efficiency and design complexity to minimize both computation and on-chip communication power. (b) We formulate an application mapping problem to mixed integer quadratic programming (MIQP) with the purpose of reducing power consumption in various hard networks and develop highly efficient algorithms for the MIQP. Regarding NoC compatible with new technologies, we focus on three dimensional (3D) die integration based on through-silicon vias (TSVs). Since an on-chip network design has been subject to not only application constraints but also design/manufacturing constraints, a 3D NoC design is required for innovation in interconnection networks. We propose a chemical-mechanical polishing (CMP) aware application-specific 3D NoC design that minimizes TSV height variation, thus reduces bonding failure, and meanwhile optimizes conventional NoC design objectives such as hop count, wirelength, power, and area. / text

Three-dimensional (3-D) system integration is believed to be a promising technology and has gained tremendous momentum in the semiconductor industry recently. The Silicon interposer is the key enabler for the 3-D systems, and is expected to have high input/output counts, fine wiring lines and many TSVs. Modeling and design of the silicon interposer can be challenging and is becoming a critical task. This dissertation mainly focuses on developing an efficient modeling approach for silicon interposers in 3-D systems. The developed numerical methods can be classified as several categories. 1. The investigation of the coupling effects in large TSV arrays in silicon interposers. The importance of coupling between TSVs for low resistivity silicon substrates is quantified both in frequency and time domains. This has been compared with high resistivity silicon substrates. 2. The development of an electromagnetic modeling approach for non-uniform TSVs. To model the complex TSV structures, an approach for modeling conical TSVs is proposed first. Later a hybrid modeling method which combines the conical TSV modeling method and cylindrical modeling method is proposed to model the non-uniform TSV structures. 3. The development of a hybrid modeling approach for power delivery networks (PDN) with through-silicon vias (TSVs). The proposed approach extends multi-layer finite difference method (M-FDM) to include TSVs by extracting their parasitic behavior using an integral equation based solver. 4. The development of an efficient approach for modeling signal paths with TSVs in silicon interposers. The proposed method utilizes the 3-D finite-difference frequency-domain (FDFD) method to model the redistribution layer (RDL) transmission lines. A new formulation on incorporating multiport networks into the 3-D FDFD formulation is presented to include the parasitic effects of TSV arrays in the system matrix. 5. The development of a 3-D FDFD non-conformal domain decomposition method. The proposed method allows modeling individual domains independently using the FDFD method with non-matching meshing grids at interfaces. This non-conformal domain decomposition method is applied to model interconnections in silicon interposer.

Nanoscale-computing fabrics based on novel materials such as semiconductor nanowires, carbon nanotubes, graphene, etc. have been proposed in recent years. These fabrics employ unconventional manufacturing techniques like Nano-imprint lithography or Super-lattice Nanowire Pattern Transfer to produce ultra-dense nano-structures. However, one key challenge that has received limited attention is the interfacing of unconventional/self-assembly based approaches with conventional CMOS manufacturing to build integrated systems. We propose a novel nanofabric approach that mixes unconventional nanomanufacturing with CMOS manufacturing flow and design rules to build a reliable nanowire-CMOS 3-D integrated fabric called N3ASICs with no new manufacturing constraints. In N3ASICs active devices are formed on a dense semiconductor nanowire array and standard area distributed pins/vias, metal interconnects route signals in 3D. The proposed N3ASICs fabric is fully described and thoroughly evaluated at all design levels. Novel nanowire based devices are envisioned and characterized based on 3D physics modeling. Overall N3ASICs fabric design, associated circuits, interconnection approach, and a layer-by-layer assembly sequence for the fabric are introduced. System level metrics such as power, performance, and density for a nanoprocessor design built using N3ASICs were evaluated and compared against a functionally equivalent CMOS design. We show that the N3ASICs version of the processor is 3X denser and 5X more power efficient for a comparable performance than the 16-nm scaled CMOS version without any new/unknown-manufacturing requirement. Systematic yield implications due to mask overlay misalignment have been evaluated. A partitioning approach to build complex circuits has been studied.

The objective of this dissertation is to derive a set of compact physical models addressing power integrity issues in high performance gigascale integration (GSI) systems and three-dimensional (3-D) systems. The aggressive scaling of CMOS integrated circuits makes the design of power distribution networks a serious challenge. This is because the supply current and clock frequency are increasing, which increases the power supply noise. The scaling of the supply voltage slowed down in recent years, but the logic on the integrated circuit (IC) still becomes more sensitive to any supply voltage change because of the decreasing clock cycle and therefore noise margin. Excessive power supply noise can lead to severe degradation of chip performance and even logic failure. Therefore, power supply noise modeling and power integrity validation are of great significance in GSI systems and 3-D systems. Compact physical models enable quick recognition of the power supply noise without doing dedicated simulations. In this dissertation, accurate and compact physical models for the power supply noise are derived for power hungry blocks, hot spots, 3-D chip stacks, and chip/package co-design. The impacts of noise on transmission line performance are also investigated using compact physical modeling schemes. The models can help designers gain sufficient physical insights into the complicated power delivery system and tradeoff various important chip and package design parameters during the early stages of design. The models are compared with commercial tools and display high accuracy.

As the convergence of multiple functions in a single electronic device drives current electronic trends, the need for increasing integration density is becoming more emphasized than in the past. To keep up with the industrial need and realize the new system integration law, three-dimensional (3-D) integration called System-on-Package (SoP) is becoming necessary. However, the commercialization of 3-D integration should overcome several technical barriers, one of which is the difficulty for the electrical design of interconnections. The 3-D interconnection design is difficult because of the modeling challenge of electrical coupling from the complicated structures of a large number of interconnections. In addition, mixed-signal design requires broadband modeling, which covers a large frequency spectrum for integrated microsystems. By using currently available methods, the electrical modeling of 3-D interconnections can be a very challenging task. This dissertation proposes a new method for constructing a broadband model of a large number of 3-D interconnections. The basic idea to address the many interconnections is using modal basis functions that capture electrical effects in interconnections. Since the use of global modal basis functions alleviates the need for discretization process of the interconnection structure, the computational cost is reduced considerably. The resultant interconnection model is a RLGC model that describes the broadband electrical behavior including losses and couplings. The smaller number of basis functions makes the interconnection model simpler, and therefore allows the generation of network parameters at reduced computational cost. Focusing on the modeling of bonding wires in stacked ICs and through-silicon via (TSV) interconnections, this research validates the interconnection modeling approach using several examples from 3-D full-wave EM simulation results.

Continued technology scaling together with the integration of disparate technologies in a single chip means that device performance continues to outstrip interconnect and packaging capabilities, and hence there exist many difficult engineering challenges, most notably in power management, noise isolation, and intra and inter-chip communication. Significant research effort spanning many decades has been expended on traditional VLSI integration technologies, encompassing process, circuit and architectural issues to tackle these problems. Recently however, three- dimensional (3-D) integration has emerged as a leading contender in the challenge to meet performance, heterogeneous integration, cost, and size demands through this decade and beyond. Through silicon via (TSV) based 3-D wafer-level integration is an emerging vertical interconnect methodology that is used to route the signal and power supply links through all chips in the stack vertically. Delay and signal integrity (SI) calculation for signal propagation through TSVs is a critical analysis step in the physical design of such systems. In order to reduce design time and mirror well established practices, it is desirable to carry this out in two stages, with the physical structures being modelled by parasitic parameters in equivalent circuits, and subsequent analysis of the equivalent circuits for the desired metric. This thesis addresses both these issues. Parasitic parameter extraction is carried out using a field solver to explore trends in typical technologies to gain an insight into the variation of resistive, capacitive and inductive parasitics including coupling effects. A set of novel closed-form equations are proposed for TSV parasitics in terms of physical dimensions and material properties, allowing the electrical modelling of TSV bundles without the need for computationally expensive field-solvers. Suitable equivalent circuits including capacitive and inductive coupling are derived, and comparisons with field solver provided values are used to show the accuracy of the proposed parasitic parameter models for the purpose of performance and SI analysis. The deep submicron era saw the interconnection delay rather than the gate delay become the major bottleneck in modern digital design. The nature of this problem in 3-D circuits is studied in detail in this thesis. The ubiquitous technique of repeater insertion for reducing propagation delay and signal degradation is examined for TSVs, and suitable strategies and analysis techniques are proposed. Further, a minimal power smart repeater suitable for global on-chip interconnects, which has the potential to reduce power consumption by as much as 20% with respect to a traditional inverter is proposed. A modeling and analysis methodology is also proposed, that makes the smart repeater easier to amalgamate in CAD flows at different levels of hierarchy from initial signal planning to detailed place and route when compared to alternatives proposed in the literature. Finally, the topic of system-level performance estimation for massively integrated systems is discussed. As designers are presented with an extra spatial dimension in 3-D integration, the complexity of the layout and the architectural trade-offs also increase. Therefore, to obtain a true improvement in performance, a very careful analysis using detailed models at different hierarchical levels is crucial. This thesis presents a cohesive analysis of the technological, cost, and performance trade-offs for digital and mixed-mode systems, outlining the choices available at different points in the design and their ramifications / QC 20100916