A novel CVD copper process is described using two new copper CVD precursors, KI3 and KI5, for the fabrication of IC or TSV (Through Silicon Via) copper interconnects. The highly conformal CVD copper can provide seed layers for subsequent copper electroplating or can be used to directly fabricate the interconnect in one step. These new precursors are thermally stable yet chemically reactive under CVD conditions, growing copper films of exceptionally high purity at high growth rates. Their thermal stability can allow for elevated evaporation temperatures to generate the high precursor vapor pressures needed for deep penetration into high aspect ratio TSV vias. Using formic acid vapor as a reducing gas with KI5, copper films of > 99.99 atomic % purity were grown at 250°C on titanium nitride at a growth rate of > 1500 Å/min. Using tantalum nitride coated TSV type wafers, ~ 1700 Å of highly conformal copper was grown at 225°C into 32 μm × 5 μm trenches with good adhesion. With ruthenium barriers we were able to grow copper at 125°C at a rate of 20 Å/min to give a continuous ~ 300 Å copper film. In this respect, rapid low temperature CVD copper growth offers an alternative to the long cycle times associated with copper ALD which can contribute to copper agglomeration occurring. © 2008 Elsevier B.V.

Novel polymer-enhanced photodefined through-silicon via (TSV) and passive technologies have been demonstrated for silicon interposers to obtain compact heterogeneous computing and mixed-signal systems. These technologies include: (1) Polymer-clad TSVs with thick (~20 µm) liners to help reduce TSV losses and stress, and obtain optical TSVs in parallel for interposer-to-interposer long-distance communication; (2) Polymer-embedded vias with copper vias embedded in polymer wells to significantly reduce the TSV losses; (3) Coaxial vias in polymer wells to reduce the TSV losses with controlled impedance; (4) Antennas over polymer wells to attain a high radiation efficiency; and (5) High-Q inductors over polymer wells. Cleanroom fabrication and characterization of the technologies have been demonstrated. For the fabricated polymer-clad TSVs, resistance and synchrotron x-ray diffraction (XRD) measurements have been demonstrated. High-frequency measurements up to 170 GHz and time-domain measurements up to 10 Gbps have been demonstrated for the fabricated polymer-embedded vias. For the fabricated coaxial vias and inductors, high-frequency measurements up to 50 GHz have been demonstrated. Lastly, for the fabricated antennas, measurements in the W-band have been demonstrated.

As the convergence of multiple functions in a single electronic device drives current electronic trends, the need for increasing integration density is becoming more emphasized than in the past. To keep up with the industrial need and realize the new system integration law, three-dimensional (3-D) integration called System-on-Package (SoP) is becoming necessary. However, the commercialization of 3-D integration should overcome several technical barriers, one of which is the difficulty for the electrical design of interconnections. The 3-D interconnection design is difficult because of the modeling challenge of electrical coupling from the complicated structures of a large number of interconnections. In addition, mixed-signal design requires broadband modeling, which covers a large frequency spectrum for integrated microsystems. By using currently available methods, the electrical modeling of 3-D interconnections can be a very challenging task. This dissertation proposes a new method for constructing a broadband model of a large number of 3-D interconnections. The basic idea to address the many interconnections is using modal basis functions that capture electrical effects in interconnections. Since the use of global modal basis functions alleviates the need for discretization process of the interconnection structure, the computational cost is reduced considerably. The resultant interconnection model is a RLGC model that describes the broadband electrical behavior including losses and couplings. The smaller number of basis functions makes the interconnection model simpler, and therefore allows the generation of network parameters at reduced computational cost. Focusing on the modeling of bonding wires in stacked ICs and through-silicon via (TSV) interconnections, this research validates the interconnection modeling approach using several examples from 3-D full-wave EM simulation results.

Continued technology scaling together with the integration of disparate technologies in a single chip means that device performance continues to outstrip interconnect and packaging capabilities, and hence there exist many difficult engineering challenges, most notably in power management, noise isolation, and intra and inter-chip communication. Significant research effort spanning many decades has been expended on traditional VLSI integration technologies, encompassing process, circuit and architectural issues to tackle these problems. Recently however, three- dimensional (3-D) integration has emerged as a leading contender in the challenge to meet performance, heterogeneous integration, cost, and size demands through this decade and beyond. Through silicon via (TSV) based 3-D wafer-level integration is an emerging vertical interconnect methodology that is used to route the signal and power supply links through all chips in the stack vertically. Delay and signal integrity (SI) calculation for signal propagation through TSVs is a critical analysis step in the physical design of such systems. In order to reduce design time and mirror well established practices, it is desirable to carry this out in two stages, with the physical structures being modelled by parasitic parameters in equivalent circuits, and subsequent analysis of the equivalent circuits for the desired metric. This thesis addresses both these issues. Parasitic parameter extraction is carried out using a field solver to explore trends in typical technologies to gain an insight into the variation of resistive, capacitive and inductive parasitics including coupling effects. A set of novel closed-form equations are proposed for TSV parasitics in terms of physical dimensions and material properties, allowing the electrical modelling of TSV bundles without the need for computationally expensive field-solvers. Suitable equivalent circuits including capacitive and inductive coupling are derived, and comparisons with field solver provided values are used to show the accuracy of the proposed parasitic parameter models for the purpose of performance and SI analysis. The deep submicron era saw the interconnection delay rather than the gate delay become the major bottleneck in modern digital design. The nature of this problem in 3-D circuits is studied in detail in this thesis. The ubiquitous technique of repeater insertion for reducing propagation delay and signal degradation is examined for TSVs, and suitable strategies and analysis techniques are proposed. Further, a minimal power smart repeater suitable for global on-chip interconnects, which has the potential to reduce power consumption by as much as 20% with respect to a traditional inverter is proposed. A modeling and analysis methodology is also proposed, that makes the smart repeater easier to amalgamate in CAD flows at different levels of hierarchy from initial signal planning to detailed place and route when compared to alternatives proposed in the literature. Finally, the topic of system-level performance estimation for massively integrated systems is discussed. As designers are presented with an extra spatial dimension in 3-D integration, the complexity of the layout and the architectural trade-offs also increase. Therefore, to obtain a true improvement in performance, a very careful analysis using detailed models at different hierarchical levels is crucial. This thesis presents a cohesive analysis of the technological, cost, and performance trade-offs for digital and mixed-mode systems, outlining the choices available at different points in the design and their ramifications / QC 20100916

Ces dernières années ont vu l'émergence d'un nouveaux concept dans le domaine de la microélectronique pour répondre aux besoins grandissant en termes de performances et taille des puces et trouver une alternative au loi de Moore et de More than Moore qui atteignent leur limites. Il s'agit de l'intégration tridimensionnelle des circuits intégrés. Cette innovation de rupture repose sur l'empilement de puces aux fonctionnalités différentes et la transmission des signaux au travers des substrats de silicium via des TSV (via traversant le silicium). Très prometteurs en termes de bande passante et de puissance consommée devant les circuits 2D, les circuits intégrés 3D permettent aussi d'avoir des facteurs de forme plus agressifs. Des points clés par rapport aux applications en vogue sur le marché (téléphonie, appareils numériques) Un prototype nommé Wide I/O DRAM réalisé à ST et au Leti a démontré ses performances face à une puce classique POP (Package on Package), avec une bande passante multipliée par huit et une consommation divisée par deux. Cependant, l'intégration de plus en plus poussée, combinée à la montée en fréquence des circuits, soulève les problèmes des diaphonies entre les interconnexions TSV et les circuits intégrés, qui se manifestent par des perturbations dans le substrat. Ces TSV doivent pouvoir véhiculer des signaux agressifs sans perturber le fonctionnement de blocs logiques ou analogiques situés à proximité, sensibles aux perturbations substrat. Cette thèse a pour objectif d'évaluer ces niveaux de diaphonies sur une large gamme de fréquence (jusqu'à 40 GHz) entre le TSV et les transistors et d'apporter des solutions potentielles pour les réduire. Elle repose sur de la conception de structure de test 3D, leur caractérisation, la modélisation des mécanismes de couplage, et des simulations. / To improve performances of integrated circuits and decrease the technology cost, designers follow “Moore's law” and “Moore than Moore law”, respectively consisting in increasing the transistor density and integrating heterogeneous circuits. This two challenges to overcome leads to a new one: the improvement of the interconnect density. In 2D circuits, the pitch of the pads is still inaccurate compared to the strong component density. Wire bonding and bumps connecting the different chips (Processor, Memory, Logic…) are long and big, leading to RC delays, losses and electrical coupling. 3D integration is a promising strategy consisting in optimizing interconnects by processing TSVs, short and high-density-allowed connections crossing the silicon bulk involving an electrically efficient way to connect the chips. To achieve high performance and reliability in 3D IC, new design rules have to be investigated because of the specific electrical, mechanical and thermal constraints for 3D stacks. Works presented focus on the high frequency substrate noise generated by high speed signals transmitted along TSVs and its impact on sensitive circuits, such as Low Noise Amplifiers. This phenomenon is a major concern for 3D circuit design and yet still lack of extraction results due to experimental difficulties in extracting noise values in a complex 3D stack. The aim of the thesis was to characterize the coupling noise between TSV and MOS devices to understand involved phenomena and to propose solutions. To raise these objectives, we studied isolated TSV, coupled TSV, TSV to wells and MOS transistor coupling through multi-physics simulations, modeling, and measurement up to 40GHz according to polarization and frequency. Specific 3D radiofrequency test structures in 4 ports have been designed for experimental characterization.

A novel CVD copper process is described using two new copper CVD precursors, KI3 and KI5, for the fabrication of IC or TSV (Through Silicon Via) copper interconnects. The highly conformal CVD copper can provide seed layers for subsequent copper electroplating or can be used to directly fabricate the interconnect in one step. These new precursors are thermally stable yet chemically reactive under CVD conditions, growing copper films of exceptionally high purity at high growth rates. Their thermal stability can allow for elevated evaporation temperatures to generate the high precursor vapor pressures needed for deep penetration into high aspect ratio TSV vias. Using formic acid vapor as a reducing gas with KI5, copper films of > 99.99 atomic % purity were grown at 250°C on titanium nitride at a growth rate of > 1500 Å/min. Using tantalum nitride coated TSV type wafers, ~ 1700 Å of highly conformal copper was grown at 225°C into 32 μm × 5 μm trenches with good adhesion. With ruthenium barriers we were able to grow copper at 125°C at a rate of 20 Å/min to give a continuous ~ 300 Å copper film. In this respect, rapid low temperature CVD copper growth offers an alternative to the long cycle times associated with copper ALD which can contribute to copper agglomeration occurring. © 2008 Elsevier B.V.

For mobile electronics such as Smartphones, Smartcards or wearable devices there is a trend towards an increasing functionality as well as miniaturisation. In this development Micro Electro- Mechanical Systems (MEMS) are an important key element for the realisation of functions such as motion detection. The specifications given by such devices together with the limited available space demand advanced packaging technologies. The 3D-Wafer Level Packaging (3D-WLP) enables one solution for a miniaturised MEMS package by using techniques such as Wafer Level Bonding (WLB) and Through Silicon Vias (TSV). This technology increases the effective area of the MEMS device by elimination dead space, which is typically required for other approaches based on wire bond assembly. Within this thesis, different TSV technology concepts with respect to a 3D-WLP for MEMS have been developed. Thereby, the focus was on a copper based technology as well as on two major TSV implementation methods. This comprises a Via Middle approach based on the separated TSV fabrication in the cap wafer as well as a Via Last approach with a TSV implementation in either the MEMS or cap wafer, respectively. For each option with its particular challenges, corresponding process modules have been developed. In the Via Middle approach, the wafer-related etch rate homogeneity determines the TSV reveal from the wafer backside Here, a reduction of the TSV depth down to 80 μm is favourable as long as the desired Cu-thermo-compression bonding (Cu-TCB) is performed before the thinning. For the TSV metallisation, a Cu electrochemical deposition method was developed, which allows the deposition of one redistribution layer as well as the bonding patterns for Cu-TCB at the same time. In the Via Last approach, the TSV isolation represents one challenge. Chemical Vapour Deposition processes have been investigated, for which a combination of PE-TEOS and SA-TEOS as well as a Parylene deposition yield the most promising results. Moreover, a method for the realisation of a suitable bonding surface for the Silicon Direct Bonding method has been developed, which does not require any wet pre treatment of the fabricated MEMS patterns. A functional MEMS acceleration sensor as well as Dummy devices serve as demonstrators for the overall integration technology as well as for the characterisation of electrical parameters. / Im Bereich mobiler Elektronik, wie z.B. bei Smartphones, Smartcards oder in Kleidung integrierten Geräten ist ein Trend zu erkennen hinsichtlich steigender Funktionalität und Miniaturisierung. Bei dieser Entwicklung spielen Mikroelektromechanische Systeme (MEMS) eine entscheidende Rolle zur Realisierung neuer Funktionen, wie z.B. der Bewegungsdetektion. Die Anforderungen derartiger Bauteile zusammen mit dem begrenzten zur Verfügung stehenden Platz erfordern neuartige Technologien für die Aufbau- und Verbindungstechnick (engl. Packaging) der Bauteile. Das 3D-Wafer Level Packaging (3D-WLP) ermöglicht eine Lösung für eine miniaturisierte MEMS-Bauform unter Nutzung von Techniken wie dem Waferlevelbonden (WLB) und den Siliziumdurchkontaktierungen (TSV von engl. Through Silicon Via). Diese Technologie erhöht die effektive aktive Fläche des MEMS Bauteils durch die Reduzierung von Toträumen, welche für andere Ansätze wie der Drahtbond-Montage üblich sind. In der vorliegenden Arbeit wurden verschiedene Technologiekonzepte für den Aufbau von 3D-WLP für MEMS erarbeitet. Dabei lag der Fokus auf einer Kupfer-basierten Technologie sowie auf zwei prinzipiellen Varianten für die TSV-Implementierung. Dies umfasst den Via Middle Ansatz, welcher auf der TSV Herstellung auf einem separaten Kappenwafer beruht, sowie den Via Last Ansatz mit einer TSV Herstellung entweder im MEMS-Wafer oder im Kappenwafer. Für beide Varianten mit individuellen Herausforderungen wurden entsprechende Prozessmodule entwickelt. Beim Via Middle Ansatz ist die Wafer-bezogene Ätzratenhomogenität des Siliziumtiefenätzen entscheidend für das spätere Freilegen der TSVs von der Rückseite. Hier hat sich eine Reduzierung der TSV-Tiefe auf bis zu 80 μm vorteilhaft erwiesen insofern, das Kupfer-Thermokompressionsbonden (Cu-TKB) vor dem Abdünnen erfolgt. Zur Metallisierung der TSVs wurde ein Cu Galvanikprozess erarbeitet, welcher es ermöglicht gleichzeitig eine Umverdrahtungsebene sowie die Bondstrukturen für das Cu-TKB zu erzeugen. Beim Via Last Ansatz ist die TSV Isolation eine Herausforderung. Es wurden CVD (Chemische Dampfphasenabscheidung) Prozesse untersucht, wobei eine Kombination aus PE-TEOS und SA-TEOS sowie eine Parylene Beschichtung erfolgversprechende Ergebnisse liefern. Des Weiteren wurde eine Methode zur Erzeugung bondfähiger Oberflächen für das Siliziumdirektbonden erarbeitet, welche eine Nass-Vorbehandlung des MEMS umgeht. Ein realer MEMS-Beschleunigungssensor sowie Testaufbauten dienen zur Demonstration der Gesamtintegrationstechnologie sowie zur Charakterisierung elektrischer Parameter.

Vertical stacking—based on modern manufacturing and integration technologies—of multiple 2D chips enables three-dimensional integrated circuits (3D ICs). This exploitation of the third dimension is generally accepted for aiming at higher packing densities, heterogeneous integration, shorter interconnects, reduced power consumption, increased data bandwidth, and realizing highly-parallel systems in one device. However, the commercial acceptance of 3D ICs is currently behind its expectations, mainly due to challenges regarding manufacturing and integration technologies as well as design automation. This work addresses three selected, practically relevant design challenges: (i) increasing the constrained reusability of proven, reliable 2D intellectual property blocks, (ii) planning different types of (comparatively large) through-silicon vias with focus on their impact on design quality, as well as (iii) structural planning of massively-parallel, 3D-IC-specific interconnect structures during 3D floorplanning. A key concept of this work is to account for interconnect structures and their properties during early design phases in order to support effective and high-quality 3D-IC-design flows. To tackle the above listed challenges, modular design-flow extensions and methodologies have been developed. Experimental investigations reveal the effectiveness and efficiency of the proposed techniques, and provide findings on 3D integration with particular focus on interconnect structures. We suggest consideration of these findings when formulating guidelines for successful 3D-IC design automation.:1 Introduction 1.1 The 3D Integration Approach for Electronic Circuits 1.2 Technologies for 3D Integrated Circuits 1.3 Design Approaches for 3D Integrated Circuits 2 State of the Art in Design Automation for 3D Integrated Circuits 2.1 Thermal Management 2.2 Partitioning and Floorplanning 2.3 Placement and Routing 2.4 Power and Clock Delivery 2.5 Design Challenges 3 Research Objectives 4 Planning Through-Silicon Via Islands for Block-Level Design Reuse 4.1 Problems for Design Reuse in 3D Integrated Circuits 4.2 Connecting Blocks Using Through-Silicon Via Islands 4.2.1 Problem Formulation and Methodology Overview 4.2.2 Net Clustering 4.2.3 Insertion of Through-Silicon Via Islands 4.2.4 Deadspace Insertion and Redistribution 4.3 Experimental Investigation 4.3.1 Wirelength Estimation 4.3.2 Configuration 4.3.3 Results and Discussion 4.4 Summary and Conclusions 5 Planning Through-Silicon Vias for Design Optimization 5.1 Deadspace Requirements for Optimized Planning of Through-Silicon Vias 5.2 Multiobjective Design Optimization of 3D Integrated Circuits 5.2.1 Methodology Overview and Configuration 5.2.2 Techniques for Deadspace Optimization 5.2.3 Design-Quality Analysis 5.2.4 Planning Different Types of Through-Silicon Vias 5.3 Experimental Investigation 5.3.1 Configuration 5.3.2 Results and Discussion 5.4 Summary and Conclusions 6 3D Floorplanning for Structural Planning of Massive Interconnects 6.1 Block Alignment for Interconnects Planning in 3D Integrated Circuits 6.2 Corner Block List Extended for Block Alignment 6.2.1 Alignment Encoding 6.2.2 Layout Generation: Block Placement and Alignment 6.3 3D Floorplanning Methodology 6.3.1 Optimization Criteria and Phases and Related Cost Models 6.3.2 Fast Thermal Analysis 6.3.3 Layout Operations 6.3.4 Adaptive Optimization Schedule 6.4 Experimental Investigation 6.4.1 Configuration 6.4.2 Results and Discussion 6.5 Summary and Conclusions 7 Research Summary, Conclusions, and Outlook Dissertation Theses Notation Glossary Bibliography / Dreidimensional integrierte Schaltkreise (3D-ICs) beruhen auf neuartigen Herstellungs- und Integrationstechnologien, wobei vor allem “klassische” 2D-ICs vertikal zu einem neuartigen 3D-System gestapelt werden. Dieser Ansatz zur Erschließung der dritten Dimension im Schaltkreisentwurf ist nach Expertenmeinung dazu geeignet, höhere Integrationsdichten zu erreichen, heterogene Integration zu realisieren, kürzere Verdrahtungswege zu ermöglichen, Leistungsaufnahmen zu reduzieren, Datenübertragungsraten zu erhöhen, sowie hoch-parallele Systeme in einer Baugruppe umzusetzen. Aufgrund von technologischen und entwurfsmethodischen Schwierigkeiten bleibt jedoch bisher die kommerzielle Anwendung von 3D-ICs deutlich hinter den Erwartungen zurück. In dieser Arbeit werden drei ausgewählte, praktisch relevante Problemstellungen der Entwurfsautomatisierung von 3D-ICs bearbeitet: (i) die Verbesserung der (eingeschränkten) Wiederverwendbarkeit von zuverlässigen 2D-Intellectual-Property-Blöcken, (ii) die komplexe Planung von verschiedenartigen, verhältnismäßig großen Through-Silicion Vias unter Beachtung ihres Einflusses auf die Entwurfsqualität, und (iii) die strukturelle Einbindung von massiv-parallelen, 3D-IC-spezifischen Verbindungsstrukturen während der Floorplanning-Phase. Das Ziel dieser Arbeit besteht darin, Verbindungsstrukturen mit deren wesentlichen Eigenschaften bereits in den frühen Phasen des Entwurfsprozesses zu berücksichtigen. Dies begünstigt einen qualitativ hochwertigen Entwurf von 3D-ICs. Die in dieser Arbeit vorgestellten modularen Entwurfsprozess-Erweiterungen bzw. -Methodiken dienen zur effizienten Lösung der oben genannten Problemstellungen. Experimentelle Untersuchungen bestätigen die Wirksamkeit sowie die Effektivität der erarbeiten Methoden. Darüber hinaus liefern sie praktische Erkenntnisse bezüglich der Anwendung von 3D-ICs und der Planung deren Verbindungsstrukturen. Diese Erkenntnisse sind zur Ableitung von Richtlinien für den erfolgreichen Entwurf von 3D-ICs dienlich.:1 Introduction 1.1 The 3D Integration Approach for Electronic Circuits 1.2 Technologies for 3D Integrated Circuits 1.3 Design Approaches for 3D Integrated Circuits 2 State of the Art in Design Automation for 3D Integrated Circuits 2.1 Thermal Management 2.2 Partitioning and Floorplanning 2.3 Placement and Routing 2.4 Power and Clock Delivery 2.5 Design Challenges 3 Research Objectives 4 Planning Through-Silicon Via Islands for Block-Level Design Reuse 4.1 Problems for Design Reuse in 3D Integrated Circuits 4.2 Connecting Blocks Using Through-Silicon Via Islands 4.2.1 Problem Formulation and Methodology Overview 4.2.2 Net Clustering 4.2.3 Insertion of Through-Silicon Via Islands 4.2.4 Deadspace Insertion and Redistribution 4.3 Experimental Investigation 4.3.1 Wirelength Estimation 4.3.2 Configuration 4.3.3 Results and Discussion 4.4 Summary and Conclusions 5 Planning Through-Silicon Vias for Design Optimization 5.1 Deadspace Requirements for Optimized Planning of Through-Silicon Vias 5.2 Multiobjective Design Optimization of 3D Integrated Circuits 5.2.1 Methodology Overview and Configuration 5.2.2 Techniques for Deadspace Optimization 5.2.3 Design-Quality Analysis 5.2.4 Planning Different Types of Through-Silicon Vias 5.3 Experimental Investigation 5.3.1 Configuration 5.3.2 Results and Discussion 5.4 Summary and Conclusions 6 3D Floorplanning for Structural Planning of Massive Interconnects 6.1 Block Alignment for Interconnects Planning in 3D Integrated Circuits 6.2 Corner Block List Extended for Block Alignment 6.2.1 Alignment Encoding 6.2.2 Layout Generation: Block Placement and Alignment 6.3 3D Floorplanning Methodology 6.3.1 Optimization Criteria and Phases and Related Cost Models 6.3.2 Fast Thermal Analysis 6.3.3 Layout Operations 6.3.4 Adaptive Optimization Schedule 6.4 Experimental Investigation 6.4.1 Configuration 6.4.2 Results and Discussion 6.5 Summary and Conclusions 7 Research Summary, Conclusions, and Outlook Dissertation Theses Notation Glossary Bibliography

For mobile electronics such as Smartphones, Smartcards or wearable devices there is a trend towards an increasing functionality as well as miniaturisation. In this development Micro Electro- Mechanical Systems (MEMS) are an important key element for the realisation of functions such as motion detection. The specifications given by such devices together with the limited available space demand advanced packaging technologies. The 3D-Wafer Level Packaging (3D-WLP) enables one solution for a miniaturised MEMS package by using techniques such as Wafer Level Bonding (WLB) and Through Silicon Vias (TSV). This technology increases the effective area of the MEMS device by elimination dead space, which is typically required for other approaches based on wire bond assembly. Within this thesis, different TSV technology concepts with respect to a 3D-WLP for MEMS have been developed. Thereby, the focus was on a copper based technology as well as on two major TSV implementation methods. This comprises a Via Middle approach based on the separated TSV fabrication in the cap wafer as well as a Via Last approach with a TSV implementation in either the MEMS or cap wafer, respectively. For each option with its particular challenges, corresponding process modules have been developed. In the Via Middle approach, the wafer-related etch rate homogeneity determines the TSV reveal from the wafer backside Here, a reduction of the TSV depth down to 80 μm is favourable as long as the desired Cu-thermo-compression bonding (Cu-TCB) is performed before the thinning. For the TSV metallisation, a Cu electrochemical deposition method was developed, which allows the deposition of one redistribution layer as well as the bonding patterns for Cu-TCB at the same time. In the Via Last approach, the TSV isolation represents one challenge. Chemical Vapour Deposition processes have been investigated, for which a combination of PE-TEOS and SA-TEOS as well as a Parylene deposition yield the most promising results. Moreover, a method for the realisation of a suitable bonding surface for the Silicon Direct Bonding method has been developed, which does not require any wet pre treatment of the fabricated MEMS patterns. A functional MEMS acceleration sensor as well as Dummy devices serve as demonstrators for the overall integration technology as well as for the characterisation of electrical parameters.:Bibliographische Beschreibung 3 Vorwort 13 List of symbols and abbreviations 15 1 Introduction 23 2 Fundamentals on MEMS and TSV based 3D integration 25 2.1 Micro Electro-Mechanical systems 25 2.1.1 Basic Definition 25 2.1.2 Silicon technologies for MEMS 26 2.1.3 MEMS packaging 29 2.2 3D integration based on TSVs 33 2.2.1 Overview 33 2.2.2 Basic processes for TSVs 34 2.2.3 Stacking and Bonding 47 2.2.4 Wafer thinning 48 2.3 TSV based MEMS packaging 50 2.3.1 MEMS-TSVs 50 2.3.2 3D-WLP for MEMS 52 3 Technology development for a 3D-WLP based MEMS 57 3.1 Target integration approach for 3D-WLP based MEMS 57 3.1.1 MEMS modules using 3D-WLP based MEMS 57 3.1.2 Integration concepts 58 3.2 Objective and requirements for the proposed 3D-WLP of MEMS 60 3.2.1 Boundary conditions 60 3.2.2 Technology concepts 63 3.3 Selected approaches for TSV implementation in MEMS 64 3.3.1 Via Last Technology 64 3.3.2 Via Middle technology 69 4 Development of process modules 75 4.1 Characterisation 75 4.2 TSV related etch processes 77 4.2.1 Equipment 77 4.2.2 Deep silicon etching 78 4.2.3 Etching of the buried dielectric layer 84 4.2.4 Patterning of TSV isolation liner – spacer etching 90 4.2.5 Summary 92 4.3 TSV isolation 93 4.3.1 Principle considerations 93 4.3.2 Experiment 95 4.3.3 Results 97 4.3.4 Summary 102 4.4 Metallisation of TSV and RDL 103 4.4.1 Plating base and experimental setup 103 4.4.2 Investigations related to the ECD process 106 4.4.3 Pattern plating 117 4.4.4 Summary 123 4.5 Wafer Level Bonding 124 4.5.1 Silicon direct bonding 124 4.5.2 Thermo-compression bonding by using ECD copper 128 4.5.3 Summary 134 4.6 Wafer thinning and TSV back side reveal 134 4.6.1 Thinning processes 134 4.6.2 TSV reveal processes 136 4.6.3 Summary 145 4.7 Under bump metallisation and solder bumps 146 5 Demonstrator design, fabrication and characterisation 149 5.1 Single wafer demonstrator for electrical test 149 5.1.1 Demonstrator design and test structure layout 149 5.1.2 Demonstrator fabrication 150 5.1.3 Electrical measurement 151 5.1.4 Summary 153 5.2 Via Last based TSV fabrication in the MEMS device wafer 153 5.2.1 Layout of the MEMS device with TSVs 153 5.2.2 Fabrication of TSVs and wafer thinning 154 5.2.3 Characterisation of the fabricated device 155 5.2.4 Summary 156 5.3 Via Last based cap-TSV for very thin MEMS devices 157 5.3.1 Design 157 5.3.2 Fabrication 158 5.3.3 Characterisation 161 5.3.4 Summary 162 5.4 Via Middle approach based on thinning after bonding 163 5.4.1 Design 163 5.4.2 Results and characterisation 164 5.4.3 Summary 166 6 Conclusion and outlook 167 Appendix A: Typical requirements on a MEMS package and its functions 171 Appendix B: Classification of packaging and system integration techniques 173 B.1 Packaging of electronic devices in general 173 B.2 Single Chip Packages 174 B.3 System integration 175 B.4 3D integration based on TSVs 180 Bibliography 183 List of figures 193 List of tables 199 Versicherung 201 Theses 203 Curriculum vitae 205 Own publications 207 / Im Bereich mobiler Elektronik, wie z.B. bei Smartphones, Smartcards oder in Kleidung integrierten Geräten ist ein Trend zu erkennen hinsichtlich steigender Funktionalität und Miniaturisierung. Bei dieser Entwicklung spielen Mikroelektromechanische Systeme (MEMS) eine entscheidende Rolle zur Realisierung neuer Funktionen, wie z.B. der Bewegungsdetektion. Die Anforderungen derartiger Bauteile zusammen mit dem begrenzten zur Verfügung stehenden Platz erfordern neuartige Technologien für die Aufbau- und Verbindungstechnick (engl. Packaging) der Bauteile. Das 3D-Wafer Level Packaging (3D-WLP) ermöglicht eine Lösung für eine miniaturisierte MEMS-Bauform unter Nutzung von Techniken wie dem Waferlevelbonden (WLB) und den Siliziumdurchkontaktierungen (TSV von engl. Through Silicon Via). Diese Technologie erhöht die effektive aktive Fläche des MEMS Bauteils durch die Reduzierung von Toträumen, welche für andere Ansätze wie der Drahtbond-Montage üblich sind. In der vorliegenden Arbeit wurden verschiedene Technologiekonzepte für den Aufbau von 3D-WLP für MEMS erarbeitet. Dabei lag der Fokus auf einer Kupfer-basierten Technologie sowie auf zwei prinzipiellen Varianten für die TSV-Implementierung. Dies umfasst den Via Middle Ansatz, welcher auf der TSV Herstellung auf einem separaten Kappenwafer beruht, sowie den Via Last Ansatz mit einer TSV Herstellung entweder im MEMS-Wafer oder im Kappenwafer. Für beide Varianten mit individuellen Herausforderungen wurden entsprechende Prozessmodule entwickelt. Beim Via Middle Ansatz ist die Wafer-bezogene Ätzratenhomogenität des Siliziumtiefenätzen entscheidend für das spätere Freilegen der TSVs von der Rückseite. Hier hat sich eine Reduzierung der TSV-Tiefe auf bis zu 80 μm vorteilhaft erwiesen insofern, das Kupfer-Thermokompressionsbonden (Cu-TKB) vor dem Abdünnen erfolgt. Zur Metallisierung der TSVs wurde ein Cu Galvanikprozess erarbeitet, welcher es ermöglicht gleichzeitig eine Umverdrahtungsebene sowie die Bondstrukturen für das Cu-TKB zu erzeugen. Beim Via Last Ansatz ist die TSV Isolation eine Herausforderung. Es wurden CVD (Chemische Dampfphasenabscheidung) Prozesse untersucht, wobei eine Kombination aus PE-TEOS und SA-TEOS sowie eine Parylene Beschichtung erfolgversprechende Ergebnisse liefern. Des Weiteren wurde eine Methode zur Erzeugung bondfähiger Oberflächen für das Siliziumdirektbonden erarbeitet, welche eine Nass-Vorbehandlung des MEMS umgeht. Ein realer MEMS-Beschleunigungssensor sowie Testaufbauten dienen zur Demonstration der Gesamtintegrationstechnologie sowie zur Charakterisierung elektrischer Parameter.:Bibliographische Beschreibung 3 Vorwort 13 List of symbols and abbreviations 15 1 Introduction 23 2 Fundamentals on MEMS and TSV based 3D integration 25 2.1 Micro Electro-Mechanical systems 25 2.1.1 Basic Definition 25 2.1.2 Silicon technologies for MEMS 26 2.1.3 MEMS packaging 29 2.2 3D integration based on TSVs 33 2.2.1 Overview 33 2.2.2 Basic processes for TSVs 34 2.2.3 Stacking and Bonding 47 2.2.4 Wafer thinning 48 2.3 TSV based MEMS packaging 50 2.3.1 MEMS-TSVs 50 2.3.2 3D-WLP for MEMS 52 3 Technology development for a 3D-WLP based MEMS 57 3.1 Target integration approach for 3D-WLP based MEMS 57 3.1.1 MEMS modules using 3D-WLP based MEMS 57 3.1.2 Integration concepts 58 3.2 Objective and requirements for the proposed 3D-WLP of MEMS 60 3.2.1 Boundary conditions 60 3.2.2 Technology concepts 63 3.3 Selected approaches for TSV implementation in MEMS 64 3.3.1 Via Last Technology 64 3.3.2 Via Middle technology 69 4 Development of process modules 75 4.1 Characterisation 75 4.2 TSV related etch processes 77 4.2.1 Equipment 77 4.2.2 Deep silicon etching 78 4.2.3 Etching of the buried dielectric layer 84 4.2.4 Patterning of TSV isolation liner – spacer etching 90 4.2.5 Summary 92 4.3 TSV isolation 93 4.3.1 Principle considerations 93 4.3.2 Experiment 95 4.3.3 Results 97 4.3.4 Summary 102 4.4 Metallisation of TSV and RDL 103 4.4.1 Plating base and experimental setup 103 4.4.2 Investigations related to the ECD process 106 4.4.3 Pattern plating 117 4.4.4 Summary 123 4.5 Wafer Level Bonding 124 4.5.1 Silicon direct bonding 124 4.5.2 Thermo-compression bonding by using ECD copper 128 4.5.3 Summary 134 4.6 Wafer thinning and TSV back side reveal 134 4.6.1 Thinning processes 134 4.6.2 TSV reveal processes 136 4.6.3 Summary 145 4.7 Under bump metallisation and solder bumps 146 5 Demonstrator design, fabrication and characterisation 149 5.1 Single wafer demonstrator for electrical test 149 5.1.1 Demonstrator design and test structure layout 149 5.1.2 Demonstrator fabrication 150 5.1.3 Electrical measurement 151 5.1.4 Summary 153 5.2 Via Last based TSV fabrication in the MEMS device wafer 153 5.2.1 Layout of the MEMS device with TSVs 153 5.2.2 Fabrication of TSVs and wafer thinning 154 5.2.3 Characterisation of the fabricated device 155 5.2.4 Summary 156 5.3 Via Last based cap-TSV for very thin MEMS devices 157 5.3.1 Design 157 5.3.2 Fabrication 158 5.3.3 Characterisation 161 5.3.4 Summary 162 5.4 Via Middle approach based on thinning after bonding 163 5.4.1 Design 163 5.4.2 Results and characterisation 164 5.4.3 Summary 166 6 Conclusion and outlook 167 Appendix A: Typical requirements on a MEMS package and its functions 171 Appendix B: Classification of packaging and system integration techniques 173 B.1 Packaging of electronic devices in general 173 B.2 Single Chip Packages 174 B.3 System integration 175 B.4 3D integration based on TSVs 180 Bibliography 183 List of figures 193 List of tables 199 Versicherung 201 Theses 203 Curriculum vitae 205 Own publications 207