Efforts to increase productivity, reduce time to market, reduce costs and desire for increased functionality on a chip are driving semiconductor companies to consider SoC (System-on-a-chip) design. SoC offers the additional benefit of improving performance and design freedom. SoC designs are smaller, energy efficient and cheaper than the multi-chip solutions. Silicon manufacturing technology has improved to an extent where one can create a reliable chip with millions of transistors. Design of these complex systems, on the other hand, is taking longer and is much costlier even when the technology allows integration of the million transistor chips. Keeping these design costs low and reducing development cycle time is vital for any chip design company. Hence, companies need to delicately balance the design costs versus benefits for SoC design. Design turn-around time (TAT) even for large complex designs has been significantly improved by EDA tools despite the complexity added by the ever shrinking device geometries. However, other non technical issues and external dependencies in SoC design such as working with multi-disciplinary design teams, external IP (Intellectual Property) vendors, Electronic Design Automation (EDA) tool vendors and IP protection issues increase the risk of missing project goals and timeline. This paper will address both the technical and non-technical issues that arise when moving to SoC design and provide recommendations on how to address some of the non-technical issues involved. / text

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Asynchronous circuits are usually applied for the communications between multiple clock-domain blocks in some SoCs. According to application-specific traffic, efficiently allocating reasonable buffers in an asynchronous NoC router can avoid the waste or shortage of buffer resource. The method of application-specific asynchronous First-In-First-Out buffer allocation can reduce the silicon area and the power consumption to improve the network latency. According to given traffic pattems, the save of area buffer of our buffer-allocation method can be up to near 30% and the latency is reduced a little at same time. / Bypass schemes is efficient to reduce the average propagation cycles in NoCs. We propose novel lookahead bypass scheme to improve the network latency. The lookahead bypass router is implemented and evaluations of valious configurations are compared, where the proposed architecture significantly improves the packet latency up to 32.1 % over a baseline router. These prove that the router can reduce the average network latency and power consumption, and decreases the reliance on large buffers and virtual channels. Furthermore, the application-specific short-circuit channel is introduced to add some short cuts in a router to bypass the crossbar switch. It can provide additional internal channels to bypass the crossbar and increase the total probability of lookahead bypass. Therefore, the latency can be further reduced. And the throughput can be increased in some applications. / Multicast is preferred in parallel computers. It is an inherent fault of network-on-chip as compared with competitor bus architecture. Software method is a conventional method to implement multicast, but there is a large overhead in latency. The latency overhead of a 4-flit multicast packet achieves 6∼7 times as compared with tree-based or path-based hardware multicast. Hardware multicast support is necessary in these applications. A group-based hardware multicast method is desclibed and estimated in this thesis. Quality of service is also introduced to speed up multicast packets. / On-chip communication infrastructures are inunensely important today. As silicon technology allows more than one billion of transistors in a single piece of silicon, the system-on-chip (SoC) circuits can contain already a large number of processing elements (PEs). Therefore, the Networks-on-Chip (NoCs) are a generally accepted concept to solve the problems such as the scalability and throughput limitation, and physical design problems inherent in dedicated links and shared buses. However, the state-of-the-art on-chip network suffers from latency overhead due to the additional network as compared with dedicated wire connection. According to the different application enviromnents, there are different low-latency technologies for networks-on-chip. This thesis proposes some methods for low-latency NoCs design to relax the latency overhead, which include application-specific asynchronous buffer allocation, hardware multicast support, lookahead bypass scheme and short-circuit crossbar channel optimization. / Xin, Ling. / Adviser: Chui-Sing Choy. / Source: Dissertation Abstracts International, Volume: 73-03, Section: B, page: . / Thesis (Ph.D.)--Chinese University of Hong Kong, 2010. / Includes bibliographical references (leaves 157-164). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [201-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstract also in Chinese.

Integrating many processing elements (PE) in a single chip is inevitable as silicon technology allows more than one billion of transistors in a single piece of silicon. Networks-on-Chip (NoCs) has been proposed as a scalable solution to both increasing bandwidth requirements and physical design problems for multi-PE chips. However, as multi-PE chips drive the design focus to shift from the computation-centric to communication-centric, area and power costs consumed by communication has become comparable to what computation consumes. / The second direction is to reduce hop counts of packets when they travel from sources to destinations, and thus to reduce power consumption of NoCs. The reduction of hop counts is realized by using a recently proposed express virtual channel (EVC) technique to virtually bypass intermediate routers. We study the EVC technique in two domains. The first domain is to present a high-level, application-specific methodology to improve power efficiency of EVC paths early in the design stage. The methodology includes three steps. Firstly, aggregate communication loads between routers are calculated. Secondly, an energy reduction model and an energy overhead model are developed. Finally, energy savings of all possible EVCs path are calculated and a greedy algorithm is applied to insert EVCs paths in an iterative way. / The second domain is to exploit the EVC flow control in design and implementation of low-power NoCs. We firstly present cost-efficient hardware components for both EVC source and EVC bypass routers, then propose a statistical approach to customize buffer architectures for EVC networks, then describe creative use of low-power circuit techniques such as clock gating and operand isolation for EVC routers, and finally evaluate EVC NoCs through detailed ASIC implementations. Results show that EVC NoCs can save up to 34.26% of power compared to baseline NoCs. / This thesis tackles design and implementation of cost-efficient NoCs along two orthogonal directions. The first direction is to reduce area and power costs of a single virtual channel router. Through ASIC implementations, we find that allocator logic, including both virtual channel allocator (VA) and switch allocator (SA), consumes a large amount of costs. Based on RTL simulations for the entire NoCs, we identify great opportunities to reduce design costs of VA and then propose two low-complexity allocators: look-ahead VA and combined switch-VC allocator (SVA). Evaluations are performed for a wide range of traffic patterns and router parameters. Results show that both proposed architectures significantly reduce area and power costs of allocators without penalties on network performances. / Zhang, Min. / Source: Dissertation Abstracts International, Volume: 72-01, Section: B, page: . / Thesis (Ph.D.)--Chinese University of Hong Kong, 2010. / Includes bibliographical references (leaves 139-145). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. Ann Arbor, MI : ProQuest Information and Learning Company, [200-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstract also in Chinese.

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Liu, Zhouyi. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2011. / Includes bibliographical references (leaves 110-114). / Abstracts in English and Chinese. / ABSTRACTS --- p.I / 摘要 --- p.II / CONTENTS --- p.III / LIST OF FIGURE --- p.V / LIST OF TABLE --- p.VI / ACKNOWLEDGEMENT --- p.VII / Chapter CHAPTER 1 --- INTRODUCTION --- p.1 / Chapter 1.1 --- NETWORK-ON-CHIP --- p.1 / Chapter 1.2 --- RELATED WORKS --- p.2 / Chapter 1.3 --- PLATFORM OVERVEW --- p.6 / Chapter 1.4 --- AUTHOR'S CONTRIBUTION --- p.10 / Chapter CHAPTER 2 --- NOC LIBRARY --- p.12 / Chapter 2.1 --- NETWORK TERMINOLOGY --- p.12 / Chapter 2.2 --- BASIC STRUCTURE --- p.15 / Chapter 2.3 --- LOW-POWER ORIENTED ARCHITECTURE --- p.20 / Chapter 2.3.1 --- Low-Cost Allocator Design --- p.21 / Chapter 2.3.2 --- Clock Gating --- p.22 / Chapter 2.3.3 --- Express Virtual Channel Insertion --- p.22 / Chapter 2.4 --- LOW-LATENCY ORIENTED ARCHITECTURE --- p.28 / Chapter 2.4.1. --- Lookahead Bypass Scheme --- p.29 / Chapter 2.4.2. --- Lookahead Bypass Router Architecture --- p.29 / Chapter CHAPTER 3 --- BENCHMARK AND MEASUREMENT --- p.31 / Chapter 3.1 --- BENCHMARK GENERATION --- p.32 / Chapter 3.1.1 --- Types of Traffic Patterns --- p.32 / Chapter 3.1.2 --- Traffic Generator --- p.36 / Chapter 3.2 --- MEASUREMENT SETTING --- p.38 / Chapter 3.2.1 --- Warming-up Period. --- p.38 / Chapter 3.2.2 --- Latency Definition --- p.39 / Chapter 3.2.3 --- Throughput Definition --- p.40 / Chapter 3.2.4 --- Virtual Channel Utilization --- p.40 / Chapter CHAPTER 4 --- PLATFORM STRUCTURE --- p.41 / Chapter 4.1 --- FILE TREE --- p.42 / Chapter 4.1.1 --- System Files --- p.46 / Chapter 4.1.2 --- Low-Power NoC Related --- p.47 / Chapter 4.1.3 --- Low-Latency NoC Related --- p.50 / Chapter 4.1.4 --- Project Related --- p.51 / Chapter 4.2 --- PROCESSES --- p.52 / Chapter 4.3 --- GUI ACCESS --- p.56 / Chapter 4.3.1 --- Section 1: Project Setup --- p.58 / Chapter 4.3.2 --- Section 2-a: Low-Power Router Structure --- p.59 / Chapter 4.3.3 --- Section 2-b: Low-Latency Router Structure --- p.60 / Chapter 4.3.4 --- Section 3: Benchmark & Measurement --- p.60 / Chapter 4.3.5 --- Section 4: View Result --- p.62 / Chapter 4.3.6 --- Low-Power NoC Example --- p.62 / Chapter CHAPTER 5 --- OPTIMIZATION AND COMPARISON --- p.72 / Chapter 5.1 --- OPTIMIZATION TECHNIQUE --- p.72 / Chapter 5.1.1 --- Optimization Phase 1: Inactive Buffer Removal --- p.73 / Chapter 5.1.2 --- Optimization Phase 2: Infighting Analysis --- p.74 / Chapter 5.1.3 --- Over-Optimization --- p.75 / Chapter 5.1.4 --- Optimization Example --- p.79 / Chapter 5.2 --- NOCS COMPARISON --- p.83 / Chapter 5.3 --- LOW-POWER IMPLEMENTATION CODE EXPORT --- p.88 / Chapter CHAPTER 6 --- SUMMARY AND FUTURE WORK --- p.92 / Chapter 6.1. --- SUMMARY --- p.92 / Chapter 6.2. --- FUTURE WORK --- p.93 / REFERENCES --- p.95

Wires have become a major source of bottleneck in current VLSI designs, and wire length prediction is therefore essential to overcome these bottlenecks. Wire length prediction is broadly classified into two types: macroscopic prediction, which is the prediction of wire length distribution, and microscopic prediction, which is the prediction of individual wire lengths. The objective of this thesis is to develop a clear understanding of limitations to both macroscopic and microscopic a priori, post-placement, pre-routing wire length predictions, and thereby develop better wire length prediction models. Investigations carried out to understand the limitations to macroscopic prediction reveal that, in a given design (i) the variability of the wire length distribution increases with length and (ii) the use of Rent’s rule with a constant Rent’s exponent p, to calculate the terminal count of a given block size, limits the accuracy of the results from a macroscopic model. Therefore, a new model for the parameter p is developed to more accurately reflect the terminal count of a given block size in placement, and using this, a new more accurate macroscopic model is developed. In addition, a model to predict the variability is also incorporated into the macroscopic model. Studies to understand limitations to microscopic prediction reveal that (i) only a fraction of the wires in a given design are predictable, and these are mostly from shorter nets with smaller degrees and (ii) the current microscopic prediction models are built based on the assumption that a single metric could be used to accurately predict the individual length of all the wires in a design. In this thesis, an alternative microscopic model is developed for the predicting the shorter wires based on a hypothesis that there are multiple metrics that influence the length of the wires. Three different metrics are developed and fitted into a heuristic classification tree framework to provide a unified and more accurate microscopic model.

Qian, Zaichen. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2010. / Includes bibliographical references (leaves 62-67). / Abstracts in English and Chinese. / Abstract --- p.i / Acknowledgement --- p.iii / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- VLSI Design Methodology --- p.1 / Chapter 1.2 --- Low Power Design --- p.6 / Chapter 1.3 --- Literature Review on Multiple Supply Voltage (MSV) --- p.10 / Chapter 1.3.1 --- Voltage Island Partitioning Problems --- p.11 / Chapter 1.3.2 --- Multiple Voltage Assignment (MVA) Problem --- p.12 / Chapter 1.4 --- Literature Review on Dynamic Voltage Scaling and Dynamic Power Management --- p.15 / Chapter 1.4.1 --- Dynamic Voltage Scaling (DVS) Problem --- p.16 / Chapter 1.4.2 --- Dynamic Power Management --- p.20 / Chapter 1.5 --- Thesis Contribution and Organization --- p.22 / Chapter 2 --- Multi-Voltage Floorplan Design --- p.24 / Chapter 2.1 --- Introduction --- p.24 / Chapter 2.2 --- Problem Formulation --- p.26 / Chapter 2.3 --- A Value-Oriented Branch-and-Bound Algorithm --- p.29 / Chapter 2.3.1 --- Branching Rules --- p.30 / Chapter 2.3.2 --- Upper Bounds --- p.31 / Chapter 2.3.3 --- Lower Bounds --- p.32 / Chapter 2.3.4 --- Pruning Rules and Value-Oriented Searching Rules --- p.33 / Chapter 2.4 --- Floorplanning --- p.35 / Chapter 2.5 --- Experimental Results --- p.36 / Chapter 2.5.1 --- Optimal Voltage Assignment --- p.37 / Chapter 2.5.2 --- Floorplanning Results --- p.38 / Chapter 3 --- Low Power Scheduling at System Level --- p.40 / Chapter 3.1 --- Introduction --- p.40 / Chapter 3.2 --- Problem Formulation --- p.42 / Chapter 3.3 --- An Optimal Offline Algorithm --- p.43 / Chapter 3.4 --- Online Algorithm --- p.46 / Chapter 3.4.1 --- Analysis on One Single Interval --- p.46 / Chapter 3.4.2 --- Online Algorithm --- p.49 / Chapter 3.4.3 --- Analysis of the Online Algorithm --- p.52 / Chapter 3.5 --- Experimental Results --- p.56 / Chapter 4 --- Conclusion and Future Work --- p.60 / Bibliography --- p.67

Off-chip interconnection networks provide for communication between processors and components within computer systems. Semiconductor process technology trends have led to the inclusion of multiple processors and components onto a single chip and recently research has focused on interconnection networks, on-chip, to connect them together. On-chip networks provide a scalable, high-bandwidth interconnect, integrated tightly with the microarchitecture to achieve high performance. On-chip networks present several new challenges, different from off-chip networks, including tighter constraints in power, area and end-to-end latency. In this dissertation, I propose interconnection network architectures that address the unique design challenges of power and end-to-end latency on chip. My work in the design, implementation and evaluation of the on-chip networks of the TRIPS project’s prototype processor, a real hardware implementation, is the foundation for my work in on-chip networking. Based on my analysis of the TRIPS on-chip networks and their workloads, I propose, design, and evaluate novel network architectures for congestion monitoring and adaptive routing that are matched to the design constraints of on-chip networks. In the TRIPS system we designed, and implemented in silicon, a distributed processor microarchitecture where traditional processor components are divided into a collection of self-contained tiles. One novel aspect of the TRIPS system is the control and data networks that the tiles use to communicate with one another. I worked on the design and implementation of one of these networks, the On-Chip Network (OCN). The OCN, a 4x10 mesh network, interconnects the tiles of the L2 cache, the two processor cores and various I/O units. Another on-chip network, the Operand Network (OPN), interconnects the execution units and serves as a bypass network, integrated tightly with the processor core. In this document I evaluate these two on-chip networks and their workloads, these evaluations serve as case studies in how on-chip design constraints affect the design of on-chip networks. In the examination of the TRIPS OCN and OPN networks, one insight we gained was that network resource imbalances can lead to congestion and poor performance. We found these imbalances are transient with time and task. Timely information about the status of the network can be used to balance the resource utilization, or reduce power. A challenge lies in providing the right information, conveyed in a timely fashion, as the metrics and methods used in off-chip networks do not map well to on-chip networks. In this document, I propose and evaluate several metrics of network congestion for their utility and feasibility in an on-chip environment. In our examination of the TRIPS on-chip networks we also found that minimizing end-to-end packet latency was critical to maintaining good system performance. Effective use of the congestion information without impact to end-to-end latency is another challenge in on-chip networking. I explore novel adaptive routing techniques that address the challenge of managing the end-to-end latency. A method that produces good results is aggregation of network status information, reducing both the bandwidth and latency required for status information transmission. In this dissertation I examine how well this technique and others compare with conventional oblivious and adaptive routing. / text