Post-silicon validation has become a critical stage in the system-on-chip (SoC) development cycle, driven by increasing design complexity, higher level of integration and decreasing time-to-market. According to recent reports, post-silicon validation effort comprises more than 50% of the overall development effort of an 65nm SoC. Though post-silicon validation covers many aspects ranging from electronic properties of hardware to performance and power consumption of whole systems, a central task remains validating functional correctness of both hardware and its integration with software. There are several key challenges to achieving accelerated and low-cost post-silicon functional validation. First, there is only limited silicon observability and controllability; second, there is no good test coverage estimation over a silicon device; third, it is difficult to generate good post-silicon tests before a silicon device is available; fourth, there is no effective software robustness testing approaches to ensure the quality of hardware/software integration. We propose a systematic approach to accelerating post-silicon functional validation with virtual prototypes. Post-silicon test coverage is estimated in the pre-silicon stage by evaluating the test cases on the virtual prototypes. Such analysis is first conducted on the initial test suite assembled by the user and subsequently on the expanded test suite which includes test cases that are automatically generated. Based on the coverage statistics of the initial test suite on the virtual prototypes, test cases are automatically generated to improve the test coverage. In the post-silicon stage, our approach supports coverage evaluation of test cases on silicon devices to ensure fidelity of early coverage evaluation. The generated test cases are issued to silicon devices to detect inconsistencies between virtual prototypes and silicon devices using conformance checking. We further extend the test case generation framework to generate and inject fault scenario with virtual prototypes for driver robustness testing. Besides virtual prototype-based fault injection, an automatic driver fault injection approach is developed to support runtime fault generation and injection for driver robustness testing. Since virtual prototype enables early driver development, our automatic driver fault injection approach can be applied to driver testing in both pre-silicon and post-silicon stages. For preliminary evaluation, we have applied our coverage evaluation and test generation to several network adapters and their virtual prototypes. We have conducted coverage analysis for a suite of common tests on both the virtual prototypes and silicon devices. The results show that our approach can estimate the test coverage with high fidelity. Based on the coverage estimation, we have employed our automatic test generation approach to generate additional tests. When the generated test cases were issued to both virtual prototypes and silicon devices, we observed significant coverage improvement. And we detected 20 inconsistencies between virtual prototypes and silicon devices, each of which reveals a virtual prototype or silicon device defect. After we applied virtual prototype-based fault injection approach to virtual prototypes for three widely-used network adapters, we generated and injected thousands of fault scenarios and found 2 driver bugs. For automatic driver fault injection, we have applied our approach to 12 widely used drivers with either virtual prototypes or silicon devices. After testing all these drivers, we found 28 distinct bugs.

As today's real-time embedded systems grow increasingly ubiquitous, rising complexity ensues as more and more functionalities are integrated. Market dynamics and competitiveness further constrict the technology-to-market time requirement, consequently pushing it to the very forefront of consideration during the development process. Traditional system development approaches could no longer efficiently cope with such formidable demands, and a paradigm shift has been perceived by many as a mandate. This thesis presents a novel platform-centric SoC design method that relies on a platform-based design to expedite the overall development process. The proposed approach offers a new perspective towards the complex systems design paradigm, and can attain the desired paradigm shift through extensive reuse and flexibility. It offers a unified communication means for all sectors involved in the development process: Semiconductor vendors can use it to publish their platform specifications; Tool vendors can use it to develop and/or enhance their tools; System developers can use it to efficiently develop the system. Key technologies are also identified, namely the Extensible Markup Language (XML) and the Unified Modeling Language (UML), that realize the proposed approach. This thesis extends XML to attain a standard means for modeling, and processing a large amount of reusable platform-related data. Additionally, it employs UML's own extension mechanism to derive a UML dialect that can be used to model real-time systems and characteristics. This UML dialect, i.e. the UML profile for Codesign Modeling Framework (UML-CMF), remains compliant to the UML standard. A sub-profile within the UML profile for Codesign Modeling Framework is also developed so as to furnish a means for efficient modeling of platforms, and that can be seamlessly integrated with other real-time modeling capabilities offered by the UML-CMF. Such an effort yields a robust UML-compliant language that is suitable for a general platform-based modeling and design. A practical use of the proposed approach is demonstrated through a powerful case study that applies the approach to develop a digital camera system. The results are comparatively presented against the SpecC approach in terms of cost metrics based on the COCOMO II model.

Reconfigurable computing architectures combine the flexibility of software with the performance of custom hardware. Such architectures are of particular interest at the nanoscale level. We argue that a bottom-up self-assembled fabric of nodes will be easier and cheaper to manufacture, however, one has to make compromises with regards to the device regularity, homogeneity, and reliability. The goal of this thesis is to evaluate the performance and cost of a self-configurable computing architecture composed of simple reconfigurable nodes for unstructured and unknown fabrics. We built a software and hardware framework for this purpose. The framework enables creating an irregular network of compute nodes where each node can be configured as a simple 2-input, 4-bit logic gate. The compute nodes are organized hierarchically by sending a packet through a top anchor node that recruits compute nodes with a chemically-inspired algorithm. The nodes are then self-configured by means of a gate-level netlist describing any digital logic circuit. A topology-agnostic optimization algorithm inspired by simulated annealing is then initiated to self-optimize the circuit for latency. Latency comparisons between non-optimized, brute-force optimized and our optimization algorithm are made. We further implement the architecture in VHDL and evaluate hardware cost, area, and energy consumption. The simple on-chip topology-agnostic optimization algorithm we propose results in a significant (up to 50\%) performance improvement compared to the non-optimized circuits. Our findings are of particular interest for emerging nano and molecular-scale circuits.

As the the number of cores on a single chip continue to grow, communication increasingly becomes the bottleneck to performance. Networks on Chips (NoC) is an interconnection paradigm showing promise to allow system size to increase while maintaining acceptable performance. One of the challenges of this paradigm is in constructing the network of inter-core connections. Using the traditional wire interconnect as long range links is proving insufficient due to the increase in relative delay as miniaturization progresses. Novel link types are capable of delivering single-hop long-range communication. We investigate the potential benefits of constructing networks with many link types applied to heterogeneous NoCs and hypothesize that a network with many link types available can achieve a higher performance at a given cost than its homogeneous network counterpart. To investigate NoCs with heterogeneous links, a multiobjective evolutionary algorithm is given a heterogeneous set of links and optimizes the number and placement of those links in an NoC using objectives of cost, throughput, and energy as a representative set of a NoC's quality. The types of links used and the topology of those links is explored as a consequence of the properties of available links and preference set on the objectives. As the platform of experimentation, the Complex Network Evolutionary Algorithm (CNEA) and the associated Complex Network Framework (CNF) are developed. CNEA is a multiobjective evolutionary algorithm built from the ParadisEO framework to facilitate the construction of optimized networks. CNF is designed and used to model and evaluate networks according to: cost of a given topology; performance in terms of a network's throughput and energy consumption; and graph-theory based metrics including average distance, degree-, length-, and link-distributions. It is shown that optimizing complex networks to cost as a function of total link length and average distance creates a power-law link-length distribution. This offers a way to decrease the average distance of a network for a given cost when compared to random networks or the standard mesh network. We then explore the use of several types of constrained-length links in the same optimization problem and find that, when given access to all link types, we obtain networks that have the same or smaller average distance for a given cost than any network that is produced when given access to only one link type. We then introduce traffic on the networks with an interconnect-based packet-level shortest-path-routed traffic model. We find heterogeneous networks can achieve a throughput as good or better than the homogeneous network counterpart using the same amount of link. Finally, these results are confirmed by augmenting a wire-based mesh network with non-traditional link types and finding significant increases the overall performance of that network.

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A large part of today's multi-core chips is interconnect. Increasing communication complexity has made new strategies for interconnects essential such as Network on Chip. Power dissipation in interconnects has become a substantial part of the total power dissipation. Hence, techniques to reduce interconnect power have become a necessity. In this thesis, we present a design methodology that gives values of bus width for interconnect links, frequency of operation for routers, in Network on Chip scenario that satisfy required throughput and dissipate minimal switching power. We develop closed form analytical expressions for the power dissipation, with bus width and frequency as variables and then use Lagrange multiplier method to arrive at the optimal values. To validate our methodology, we implement the router design in 90 nm technology and measure power for various bus widths and frequency combinations. We find that the experimental results are in good agreement with the predicted theoretical results. Further, we present the scenario of an Application Specific System on Chip (ASSoC), where the throughput requirements are different on different links. We show that our analytical model holds in this case also. Then, we present modified version of the solution considered for Chip Multi Processor (CMP) case that can solve the ASSoC scenario also.

The heterogenous nature and the demand for extensive parallel processing in modern applications have resulted in widespread use of Multicore System-on-Chip (SoC) architectures. The emerging Network-on-Chip (NoC) architecture provides an energy-efficient and scalable communication solution for Multicore SoCs, serving as a powerful replacement for traditional bus-based solutions. The key to successful realization of such architectures is a flexible, fast and robust emulation platform for fast design space exploration. In this research, we present the design and evaluation of a highly configurable NoC used in AcENoCs (Accelerated Emulation platform for NoCs), a flexible and cycle accurate field programmable gate array (FPGA) emulation platform for validating NoC architectures. Along with the implementation details, we also discuss the various design optimizations and tradeoffs, and assess the performance improvements of AcENoCs over existing simulators and emulators. We design a hardware library consisting of routers and links using verilog hardware description language (HDL). The router is parameterized and has a configurable number of physical ports, virtual channels (VCs) and pipeline depth. A packet switched NoC is constructed by connecting the routers in either 2D-Mesh or 2D-Torus topology. The NoC is integrated in the AcENoCs platform and prototyped on Xilinx Virtex-5 FPGA. The NoC was evaluated under various synthetic and realistic workloads generated by AcENoCs' traffic generators implemented on the Xilinx MicroBlaze embedded processor. In order to validate the NoC design, performance metrics like average latency and throughput were measured and compared against the results obtained using standard network simulators. FPGA implementation of the NoC using Xilinx tools indicated a 76% LUT utilization for a 5x5 2D-Mesh network. A VC allocator was found to be the single largest consumer of hardware resources within a router. The router design synthesized at a frequency of 135MHz, 124MHz and 109MHz for 3-port, 4-port and 5-port configurations, respectively. The operational frequency of the router in the AcENoCs environment was limited only by the software execution latency even though the hardware itself could be clocked at a much higher rate. An AcENoCs emulator showed speedup improvements of 10000-12000X over HDL simulators and 5-15X over software simulators, without sacrificing cycle accuracy.

Optofluidics is a new branch within photonics which attempts to unify concepts from optics and microfluidics. Unification of photonics and microfluidics enable us to carry out analysis of fluids through highly sensitive optical sensing device. These optical sensing devices are contained within a microchip, wherein light is made to pass through analyte (fluids of few nanoliters). The interaction between light and fluid gives rise to highly sensitive diagnostic systems. In this work the fabrication and performance characterization of a fluorescent green OLED for optofluidic applications is presented. The effect of thickness variation of hole injection (CuPc) and hole blocking (BCP) layers on the performance of fluorescent green organic light emitting diodes (OLEDs) have been studied. Even though these two organic layers have opposite functions, yet there is a particular combination of their thicknesses when they function in conjunction and luminous efficiency and power efficiency are maximized. The optimum thickness of CuPc layer, used as hole injection layer and BCP used as hole blocking layer were found to be 18 nm and 10 nm respectively. It is with this delicate adjustment of thicknesses, charge balancing was achieved and luminous efficiency and power efficiency were optimized. Such OLEDs with higher luminance can be monolithically integrated with other optical and fluidic components on a common substrate and can function as monolithically integrated internal source of light in optofluidic sensors. In this work the analysis of a fully integrated optofluidic lab-on-a-chip sensor for refractive index and absorbance based sensing using fluorescent green organic light emitting diode (OLED) as a light source is also presented. This device consists of collinear input and output waveguides which are separated by a microfluidic channel. When light is passed through the analyte contained in the fluidic gap an optical power loss due to absorption of light takes place. Apart from absorption a mode-mismatch between collinear input and output waveguide also occurs. The degree of mode-mismatch, quantum of optical power loss due to absorption of light by the fluid forms the basis of our analysis. Detection of minutest change in refractive index and changes in concentration of species contained in the analyte is indicative of sensitivity. Various parameters which influence the sensitivity of the sensor are mode spot size, refractive index of the fluid, molar concentration of the species contained in the analyte, width of the fluidic gap, waveguide geometry. By correlating various parameters, an optimal fluidic gap distance corresponding to a particular mode spot size to achieve the best sensitivity for refractive index based sensing and absorbance based sensing have been determined.

Breitstreifenlaser haben eine breite Emissionsapertur, die es ermöglicht eine hohe Ausgangsleistung zu erreichen. Gleichzeitig führt sie jedoch zu einer Verringerung der lateralen Strahlqualität und zu ihrem nicht-stationären Verhalten. Forschung in diesem Gebiet ist anwendungsgetrieben und somit ist das Hauptziel eine Erhöhung der Brillanz, die sowohl die Ausgangsleistung als auch die laterale Strahlqualität beinhaltet. Um die zugrunde liegenden raumzeitlichen Phänomene zu verstehen und dieses Wissen zu nutzen, um die Kosten der Brillanz-Optimierung zu minimieren, ist ein selbst-konsistentes Simulationstool notwendig, welches die wichtigsten Prozesse beinhaltet. Zunächst wird in dieser Arbeit ein quasi-dreidimensionales elektro-optisch-thermisches Model präsentiert, welches wesentliche qualitative Eigenschaften von realen Bauteilen gut beschreibt. Zeitabhängige Wanderwellen-Gleichungen werden genutzt, um die inhärent nicht-stationären optischen Felder zu beschreiben, welche an eine Ratengleichung für die Überschussladungsträger in der aktiven Zone gekoppelt sind. Das Model wird in dieser Arbeit um eine Injektionsstromdichte erweitert, die laterale Stromspreizung und räumliches Lochbrennen korrekt beschreibt. Des Weiteren wird ein Temperaturmodel präsentiert, das kurzzeitige lokale Aufheizungen in der Nähe der aktiven Zone und die Formierung einer stationären Temperaturverteilung beinhalten. Im zweiten Teil wird das beschriebene Modell genutzt, um die Gründe von Brillanz-Degradierung, das heißt sowohl die Ursprünge der Leistungssättigung als auch des nicht diffraktionslimitierten Fernfeldes zu untersuchen. Abschließend werden im letzten Teil Laserentwürfe besprochen, welche die laterale Brillanz verbessern. Hierzu gehört ein neuartiges “Schachbrettlaser” Design, bei dem longitudinal-laterale Gewinn-Verlust-Modulation mit zusätzlicher Phasenanpassung ausgenutzt wird, um eine sehr geringe Fernfeld-Divergenz zu erhalten. / Broad-area lasers are edge-emitting semiconductor lasers with a wide lateral emission aperture that enables high output powers, but also diminishes the lateral beam quality and results in their inherently non-stationary behavior. Research in the area is driven by application and the main objective is to increase the brightness which includes both the output power and lateral beam quality. To understand the underlying spatio-temporal phenomena and to apply this knowledge in order to reduce costs for brightness optimization, a self-consistent simulation tool taking into account all essential processes is vital. Firstly, in this work a quasi-three-dimensional opto-electronic and thermal model is presented, that describes well essential qualitative characteristics of real devices. Time-dependent traveling-wave equations are utilized to describe the inherently non-stationary optical fields, which are coupled to dynamic rate equations for the excess carriers in the active region. This model is extended by an injection current density model to accurately include lateral current spreading and spatial hole burning. Furthermore a temperature model is presented that includes short-time local heating near the active region as well as the formation of a stationary temperature profile. Secondly, the reasons of brightness degradation, i.e. the origins of power saturation and the spatially modulated field profile are investigated and lastly, designs that mitigate those effects that limit the lateral brightness under pulsed and continuous-wave operation are discussed. Amongst those designs a novel “chessboard laser” is presented that utilizes longitudinal-lateral gain-loss modulation and an additional phase tailoring to obtain a very low far-field divergence.