Power line communications (PLC) has been considered by utility companies for over a half century and for home networking in recent years. However, PLC at the IC level, or even at the PCB level, has not been investigated outside Dr. Ha's research group. This thesis investigates the feasibility of PLC over power distribution networks (PDNs) of advanced microprocessors. A PDN in an integrated circuit (IC) is ubiquitous as seen by the internal logic, i.e., a power line is accessible to any internal node. This suggests the possibility of monitoring or controlling the logic value of any internal node through a power line by attaching a simple sensing/control circuit to the node. Routing the data through a power line avoids the necessity of preplanning the routing of a data path between the node and an external data pin. PLC over microprocessor PDNs also provide a viable means for "run-time testing" as well as for monitoring the so called "large time-constant errors" resulting from aging and temperature variations. In this thesis, we considered impulse-based ultra wideband (I-UWB) communication technology for PLC over PDNs of microprocessors. I-UWB has several advantages for PLC over PDNs due to its robustness to multipath effects, simple hardware for transmission and reception of pulses and, more importantly, reduced interference to the normal operation of microprocessors. A microprocessor PDN is heavily decoupled to damp the resonances in the power supply impedance as well as to reduce the slew rate of current variations by locally supplying (sinking) currents to (from) the switching nodes. Consequently, a PDN behaves like a bulky lowpass filter for high frequency signals. However, the inductance component of decoupling capacitors becomes more significant beyond the self resonant frequency (SRF) of the capacitors. So, a PDN becomes essentially a distributed circuit beyond the SRF and is no longer a lowpass filter. Indeed, high frequency PDN models developed earlier at Dr. Ha's group show that there exist multiple frequency bands where high frequency signals can propagate through the PDN with relatively low attenuation [3] [4]. The major contributions of our research lie in three areas. First, we verified existence of passbands on PDN's transfer characteristics through measurements. We carried out high frequency measurements on the PDN of Intel's 65 nm Pentium processor and 45 nm Core 2 Duo processor. We measured PDN transfer characteristics up to several GHz from a core power pin on a tester board to an on-chip power node for both active and cold microprocessor dies. The measurements show the existence of narrow, sporadic and migratory passbands i.e. location of passbands change from one generation of processor to the next. The migratory nature of passbands requires the I-UWB receiver and a transmitter to cover a wide range of frequencies rather than a specific passband. Second, we have developed a PDN communication channel model for system level study. To develop the channel model, we also performed noise measurements on Intel microprocessors. The link budget was calculated based on the channel model and appropriate modulation schemes were suggested through the system level study. Third, we investigated design of an I-UWB receiver and a transmitter, which cover a wide bandwidth. The proposed receiver and transmitter designs were evaluated through simulations in TSMC 0.18 μm CMOS process. Our simulation indicates that the PLC over a PDN is feasible with a relatively simple digital-process friendly I-UWB receiver and a transmitter. / Ph. D.

Power line communications (PLC) as applied to electrical power grid is known since long; however, PLC in microprocessors was recently introduced by VTVT Lab. Since power distribution network (PDN) inside a microprocessor is ubiquitous, therefore, any node inside a microprocessor can be accessed by attaching a simple communication circuit to it. The scheme is extremely attractive as it avoids the routing overhead of the data-path between an internal node and an I/O pin. A number of applications are possible for PLC in microprocessors such as on-line testing, monitoring/control of internal nodes, fault diagnosis etc. Feasibility of the PLC approach has been extensively studied by earlier researchers at VTVT. The feasibility studies investigated the frequency response of a microprocessor's PDN and looked for existence of passbands — frequency bands where signal attenuation through the PDN is small. Two different approaches were followed—the first approach employed analytical modeling of the high frequency characteristics of the PDN, while the second approach conducted measurements on Intel® microprocessors' PDN. Although, differences were observed in the results of the two approaches; both the approaches demonstrated existence of passbands, thus affirming the feasibility of the PLC scheme. This thesis presents a system level study conducted to estimate performance of the PLC scheme. Measurement results were used to model the PDN channel. The study provides useful insights for the design of microprocessor level PLC system. Specifically, the study estimates optimal pulse width required to maximize the system performance and the range of achievable data-rates. The study demonstrates that it is feasible to communicate data through a microprocessor's PDN without inducing large disturbances on the power line. The other work presented in this thesis is the design of low power receiver for microprocessor level PLC, also called data recovery block. The proposed design of data recovery block employs Correlation Detection (CD) receiver architecture. The design has been implemented in IBM 0.13 µm CMOS process and has been verified to operate reliably across Process, Voltage and Temperature variations. The design has a small foot-print of 300 µm x 160 µm and consumes 3.58 mW while operating from 1.2 V power supply. / Master of Science

A silicon interposer platform with microfluidic cooling is proposed for high-performance computing systems. The key components and technologies for the proposed platform, including electrical and fluidic microbumps, microfluidic vias and heat sinks, and simultaneous flip-chip bonding of the electrical and fluidic microbumps, are developed and demonstrated. Fine-pitch electrical microbumps of 25 µm diameter and 50 µm pitch, fluidic vias of 100 µm diameter, and annular-shaped fluidic microbumps of 150 µm inner diameter and 210 µm outer diameter were fabricated and bonded. Electrical and fluidic tests were conducted to verify the bonding results. Moreover, the thermal and signaling benefits of the proposed platform were evaluated based on thermal measurements and simulations, and signaling simulations. Compared to the conventional air cooling, significant reductions in system temperature and thermal coupling are achieved with the proposed platform. Moreover, the signaling performance is improved due to the reduced temperature, especially for long interconnects on the silicon interposer. A numerical power distribution network (PDN) simulator is developed based on distributed circuit models for on-die power/ground grids, package- and board- level power/ground planes, and the finite difference method. The simulator enables power supply noise simulation, including IR-drop and simultaneous switching noise, for a full chip with multiple blocks of different power, decoupling capacitor, and power/ground pad densities. The distributed circuit model is further extended to include TSVs to enable simulations for 3D PDN. The integration of package- and board- level power/ground planes enables co-simulation of die-package-board PDN and exploration of new PDN configurations.

The main purpose of this thesis was to develop a printed circuit board for Autoliv Electronics AB. This circuit board should be placed in their test equipment to support some of their camera vision systems used in cars. The main task was to combine the existing hardware into one module. To be able to achieve this, the most important factors in designing a printed circuit board was considered. A satisfying power distribution network is the most crucial one. This was accomplished by using decoupling capacitors to achieve low enough impedance for all circuits. Calculations and simulations were executed for all integrated circuits to find the correct size and numbers of capacitors. The impedance of the circuit board was tested with a network analyzer to confirm that the impedance were low enough, which was the case. System functionality was never tested completely, due to delivery problems with some external equipment.

We have proposed a method by which the topology of a network might be discovered through an algorithm like the distributed Bellman-Ford algorithm. We have explored the inner workings of two methods to automate power distribution network reconfiguration, the ILP Solver and the Heuristic Solver. We have seen how networks of different shapes can be translated into a flattened topology, which is necessary preprocessing to find a power assignment solution for a network. We have also seen some experimental results comparing the performance of the ILP Solver and the Heuristic Solver. The Heuristic Solver is a very fast, efficient algorithm to reconfigure power distribution, which is important in the case of an emergency. It performs consistently with near perfect results at a speed that is orders of magnitude quicker than the ILP Solver in almost all cases. In an application where a network is small and time is not an important constraint, the ILP Solver could possibly be preferable, but in any context where time is sensitive and near-perfect results are as acceptable as perfect results, the Heuristic Solver is much preferable. There is always room for improvement. Future tests should perhaps allow for non-integer capacity units, or loads that require other values than unit capacity. Optimizing each algorithm by rewriting them in C could give more optimized tests, though this may not be necessary to make judgments about implementing one or the other. There may be some ways to improve the Heuristic Solver, such as arranging the ordered_links in some way that could be more optimal. The algorithm could also be improved by taking advantage of the fact that once there are no more sources with capacity to provide any loads, the process of trying to assign loads to them for power supply can cease. Perhaps this method could be combined with other methods that do not presently account for load priorities or place as much value on fast execution.

Reliability is one of the important issues of recent microprocessor design. Processors must provide correct behavior as users expect, and must not fail at any time. However, unreliable operation can be caused by excessive supply voltage fluctuations due to an inductive part in a microprocessor power distribution network. This voltage fluctuation issue is referred to as inductive or di/dt noise, and requires thorough analysis and sophisticated design solutions. This dissertation proposes an automated stressmark generation framework to characterize di/dt noise effect, and suggests a practical solution for management of di/dt effects while achieving performance and energy goals. First, the di/dt noise issue is analyzed from theory to a practical view. Inductance is a parasitic part in power distribution network for microprocessor, and its characteristics such as resonant frequencies are reviewed. Then, it is shown that supply voltage fluctuation from resonant behavior is much harmful than single event voltage fluctuations. Voltage fluctuations caused by standard benchmarks such as SPEC CPU2006, PARSEC, Linpack, etc. are studied. Next, an AUtomated DI/dT stressmark generation framework, referred to as AUDIT, is proposed to identify maximum voltage droop in a microprocessor power distribution network. The di/dt stressmark generated from AUDIT framework is an instruction sequence, which draws periodic high and low current pulses that maximize voltage fluctuations including voltage droops. AUDIT uses a Genetic Algorithm in scheduling and optimizing candidate instruction sequences to create a maximum voltage droop. In addition, AUDIT provides with both simulation and hardware measurement methods for finding maximum voltage droops in different design and verification stages of a processor. Failure points in hardware due to voltage droops are analyzed. Finally, a hardware technique, floating-point (FP) issue throttling, is examined, which provides a reduction in worst case voltage droop. This dissertation shows the impact of floating point throttling on voltage droop, and translates this reduction in voltage droop to an increase in operating frequency because additional guardband is no longer required to guard against droops resulting from heavy floating point usage. This dissertation presents two techniques to dynamically determine when to tradeoff FP throughput for reduced voltage margin and increased frequency. These techniques can work in software level without any modification of existing hardware. / text

The objective of this dissertation is to develop electrical modeling and co-simulation methodologies for signal and power integrity of package and board applications. The dissertation includes 1) the application of the finite element method to the optimization for decoupling capacitor selection and placement on a power delivery network (PDN), 2) the development of a PDN modeling method effective for multidimensional and multilayer geometries, 3) the analysis and modeling of return path discontinuities (RPDs), and 4) the implementation of the absorbing boundary condition for PDN modeling. The optimization technique for selection and placement of decoupling capacitors uses a genetic algorithm (GA) and the multilayer finite element method (MFEM), a PDN modeling method using FEM. The GA is customized for the decoupling problem to enhance the convergence speed of the optimization. The mathematical modifications necessary for the incorporation of the capacitor model into MFEM is also presented. The main contribution of this dissertation is the development of a new modeling method, the multilayer triangular element method (MTEM), for power/ground planes of a PDN. MTEM creates a surface mesh on each plane-pair using dual graphs; a non-uniform triangular mesh (Delaunay triangulation) and its orthogonal counterpart (Voronoi diagram), to which electromagnetic and equivalent circuit concepts are applied. The non-uniform triangulation is especially efficient for discretizing multidimensional and irregular geometries which are common in package and board PDNs. Moreover, MTEM generates a sparse, banded, and symmetric system matrix, which enables efficient computations. For a given plane-pair, MTEM extracts an equivalent circuit that is consistent with the physics-based planar-circuit model of a plane-pair. Thus, the values of the lumped elements can be simply calculated from the physical parameters, such as material properties and mesh geometries of each unit-cell. Consequently, the modeling of MTEM is flexible and easy to modify for further extensions, such as the incorporation of external circuits, e.g. decoupling capacitors and vertical interconnects. Power and ground planes provide paths for the return current of signal traces. Typically, planes have discontinuities such as via holes, plane cutouts, and split planes that disturb flow of signal return currents. At the discontinuity, return currents have to detour or switch to different layers, causing signal and power integrity problems. Therefore, a separate analysis of signal interconnects will neglect the significant coupling with a PDN, and the result will not be reliable. In this dissertation, the co-simulation of the signal and power integrity is presented focusing on the modeling of RPDs created by split planes, apertures, and vias. Plane resonance is one of the main sources of power integrity problems in package and board PDNs. A number of techniques have been developed and published in literature to reduce or prevent the resonance of a plane-pair. One of the techniques is to surround plane-pair edges with absorbing material that effectively damps the outgoing parallel-plate wave and minimizes the reflection. To model this behavior, the boundary condition of MTEM needs to be changed from its original form, the open-circuit boundary condition. In this dissertation, the application of the 1st order absorbing boundary condition to MTEM is presented.

Power supply noise, which is the variation in the supply voltage across the on-die supply terminals of VLSI circuits, is a serious performance degrader in digital circuits and mixed analog-digital circuits. In digital VLSI systems, power supply noise causes timing errors such as delays, jitter, and false switching. In microprocessors, power supply noise reduces the maximum operating frequency (FMAX) of the CPU. In mixed analog-digital circuits, power supply noise manifests as the substrate noise and impairs the performance of the analog portion. The decrease in the available noise margin with the decrease in the feature size of transistors in CMOS systems makes the power supply noise a very serious issue, and demands new methods to reduce the power supply noise in sub-micron CMOS systems. In this thesis, we develop a new method to determine optimal time-delays between the switching of input/output (I/O) data buffers in digital VLSI systems that realizes maximum reduction of the power supply noise. We first discuss methods to characterize the distributed nature of the Power Delivery Network (PDN) in the frequency-domain. We then develop an analytical method to determine the optimal delays using the frequency-domain response of the PDN and the supply current spectrum of the buffer units. We explain the mechanism behind the cancellation of the power supply noise by the introduction of optimal buffer-to-buffer delays. We also develop a numerical method to determine the optimal delays and compare it with the analytical method. We illustrate the reduction in the power supply noise by applying the optimal time-delays determined using our methods to two examples of PDN. Our method has great potential to realize maximum reduction of power supply noise in digital VLSI circuits and substrate noise in mixed analog-digital VLSI circuits. Lower power supply noise translates into lower cost and improved performance of the circuit.

Στην παρούσα Διπλωματική Εργασία μελετάται και αναλύεται η Ηλεκτρομαγνητική συμπεριφορά βασικών κυκλωμάτων και στοιχείων, τα οποία απαντώνται πάνω σε Πλακέτες Τυπωμένων Κυκλωμάτων. Η σχεδίαση και ανάλυση των μοντέλων γίνεται χρησιμοποιώντας τα Ηλεκτρομαγνητικά λογισμικά πακέτα της Agilent, ΕΜPro και ADS, ενώ για τον υπολογισμό χρήσιμων παραμέτρων χρησιμοποιείται η ελεύθερη εφαρμογή της Agilent, Appcad και η εφαρμογή Linecalc, η οποία είναι ενσωματωμένη στο ADS. Αρχικά, γίνεται μια σύντομη αναφορά στις σύγχρονες τάσεις που επικρατούν στην περιοχή των Τυπωμένων Κυκλωμάτων και περιγράφεται η χρησιμότητα των τοπολογιών που αναλύονται. Επιπροσθέτως, αναφέρεται η αναγκαιότητα και οι περιπτώσεις κατά τις οποίες είναι απαραίτητη η διεξαγωγή ηλεκτρομαγνητικής ανάλυσης των κυκλωμάτων, αλλά και τα προτερήματα που αυτή προσφέρει. Παρουσιάζεται η χρησιμότητα και αναλύεται η δομή μιας μαιανδρικής μικροταινιακής γραμμής εισαγωγής καθυστερήσεως και συγκρίνονται οι εκπομπές της ως προς τις εκπομπές μιας ευθείας μικροταινιακής γραμμής. Έπειτα, μελετάται η κατανομή του ρεύματος στο επίπεδο αναφοράς μιας απλούστερης γεωμετρίας μαιανδρικής μικροταινιακής γραμμής και παρουσιάζονται φαινόμενα περισσότερο αισθητά σε υψηλές συχνότητες. Έπειτα, μελετώνται οι εκπομπές από μια γεωμετρία μικροταινιακής γραμμής, η οποία διασχίζει σχισμή στο επίπεδο αναφοράς. Επίσης, μελετάται η συμπεριφορά μικροταινιακής γραμμής ευρισκόμενης στο χείλος μιας πλακέτας. Επιπλέον, μελετάται ένα πρόβλημα σχεδιάσεως αποτελεσματικής ηλεκτρομαγνητικής θωρακίσεως και υπολογίζεται η αποδοτικότης της θωρακίσεως. Σε επόμενο κεφάλαιο, μελετάται η επίδραση ασυνεχειών ευρισκόμενων σε μια δομή μικροταινιακής γραμμής και σχεδιάζεται ένα μεταϋλικό, ενώ παράλληλα προσδιορίζονται χαρακτηριστικές παράμετροι της δομής. Ακολούθως, σχεδιάζονται τρία είδη δομών που περιλαμβάνουν οπές via. Αυτές είναι: μία απλή via , μια δομή διαφορικών via και μια εφαρμογή απομονώσεως δυο συζευγμένων ταινιογραμμών χρήσει ενός φράχτη από οπές via. Τέλος, προσομοιώνεται η λειτουργία μιας πραγματικής πλακέτας και υπολογίζονται οι ηλεκτρομαγνητικές της εκπομπές στο μακρινό πεδίο. Παράλληλα, παρουσιάζονται ορισμένα στατιστικά του χρόνου εκτελέσεως και των απαιτούμενων πόρων για την προσομοίωση, γίνονται σχόλια και επισημάνσεις που αφορούν στα χαρακτηριστικά των χρησιμοποιούμενων αλγορίθμων για τη διεξαγωγή μετεπεξεργασίας των δεδομένων και δίνονται χρήσιμες συμβουλές όσον αφορά σε χαρακτηριστικά του λογισμικού Προσομοιώσεως και σε δυνατότητες επιταχύνσεως της Προσομοιώσεως που προσφέρονται από το ίδιο το λογισμικό. / -

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