Reliability is one of the important issues of recent microprocessor design. Processors must provide correct behavior as users expect, and must not fail at any time. However, unreliable operation can be caused by excessive supply voltage fluctuations due to an inductive part in a microprocessor power distribution network. This voltage fluctuation issue is referred to as inductive or di/dt noise, and requires thorough analysis and sophisticated design solutions. This dissertation proposes an automated stressmark generation framework to characterize di/dt noise effect, and suggests a practical solution for management of di/dt effects while achieving performance and energy goals. First, the di/dt noise issue is analyzed from theory to a practical view. Inductance is a parasitic part in power distribution network for microprocessor, and its characteristics such as resonant frequencies are reviewed. Then, it is shown that supply voltage fluctuation from resonant behavior is much harmful than single event voltage fluctuations. Voltage fluctuations caused by standard benchmarks such as SPEC CPU2006, PARSEC, Linpack, etc. are studied. Next, an AUtomated DI/dT stressmark generation framework, referred to as AUDIT, is proposed to identify maximum voltage droop in a microprocessor power distribution network. The di/dt stressmark generated from AUDIT framework is an instruction sequence, which draws periodic high and low current pulses that maximize voltage fluctuations including voltage droops. AUDIT uses a Genetic Algorithm in scheduling and optimizing candidate instruction sequences to create a maximum voltage droop. In addition, AUDIT provides with both simulation and hardware measurement methods for finding maximum voltage droops in different design and verification stages of a processor. Failure points in hardware due to voltage droops are analyzed. Finally, a hardware technique, floating-point (FP) issue throttling, is examined, which provides a reduction in worst case voltage droop. This dissertation shows the impact of floating point throttling on voltage droop, and translates this reduction in voltage droop to an increase in operating frequency because additional guardband is no longer required to guard against droops resulting from heavy floating point usage. This dissertation presents two techniques to dynamically determine when to tradeoff FP throughput for reduced voltage margin and increased frequency. These techniques can work in software level without any modification of existing hardware. / text

Earlier designs were driven by the goal of achieving higher performance, but lately, energy efficiency has emerged as an even more important design principle. Strong demand from the consumer electronics drives research in the low power and energy-efficient methodologies. Moreover, with exponential increase in the number of transistors on a chip and with further technology scaling, variability in the design is now of greater concern. Variations can make the design unreliable or the design may suffer from sub-optimal performance. Through the work in this thesis, we present a multi-dimensional investigation into the design of variation aware energy-efficient systems. Our overarching methodology is to use system-level decisions to mitigate undesired effects originating from device-level and circuit-level issues. We first look into the impact of process variation (PV) on energy efficient, scalable throughput many-core DSP systems. In our proposed methodology, we leverage the benefits of aggressive voltage scaling (VS) for obtaining energy efficiency while compensating for the loss in performance by exploiting parallelism present in various DSP designs. We demonstrate this proposed methodology consumes 8% - 77% less power as compared to simple dynamic VS over different workload environments. Later, we show judicious system-level decisions, namely, number of cores, and their operating voltage can greatly mitigate the effects of PV and consequently, improve the energy efficiency of the design. We also present our analysis discussing the impact of aging on the proposed methodology. To validate our proposed system-level approach, design details of a prototype chip fabricated in the 90nm technology node and its findings are also presented. The chip consists of 8 homogeneous FIR cores, which are capable of running from near-threshold to nominal voltages. In the 20-chip population, we observe 7% variation in the speed at nominal voltage (0.9V) and 26% at near threshold voltage (0.55V) among all the cores. We also observe 54% variation in power consumption characteristics of the cores. The chip measurement results show that our proposed methodology of judiciously selecting the cores and their operating voltage can result in 6.27% - 28.15% more energy savings for various workload environments, as compared to globally voltage scaled systems. Furthermore, we present the impact of temperature variations on the energy-efficiency of the above systems. We also study the problem of voltage variations in the integrated circuits. We first present the characteristics of a dynamic voltage noise as measured on a 28nm FPGA. We propose a fully digital on-chip sensor that can detect the fast voltage transients and alert the system of voltage emergency. A traditional approach to mitigate this problem is to use safety guardbands. We demonstrate that our proposed sensor system will be 6% - 27.5% more power efficient than the traditional approach. / Ph. D.

Silicon Carbide as a wide-bandgap semiconductor has several physical and electrical advantages over Silicon for high voltage and high frequency applications. SiC as a MOSFET device has a lot of great characteristics like lower on-resistance and low input capacitances. However, due to its high switching capabilities, SiC MOSFET-based converter circuits experience higher dv/dt and di/dt transients and are therefore more susceptible to parasitic elements. This thesis investigates the interaction of the parasitic gate inductance and resistance on the switching behaviour of SiC DMOSFET (planar) and UMOSFET (trench). To examine this, a double pulse test (DPT) setup was utilised both in simulation and experimentally. The influence of the gate inductance and resistance on the oscillation behaviour in the VGS during the miller period was found to be dependent on the condition of the upper device. Furthermore, the upper device was discovered to have a high impact on the oscillations in the VGS via its source inductance. The gate inductance showed a mixed impact on IDS and VDS overshoot, with IDS overshoot reducing with increasing gate inductance and the reverse case for VDS. The gate resistance, however, showed a consistent impact on both IDS and VDS overshoot, with both reducing with increasing gate resistance. These results ultimately point to the impact of di/dt and dv/dt transients. An interesting result observed on these root causes showed that in the DPT arrangement used, lower test current levels may have a more significant impact on the oscillations in the VGS than higher test current when varying the test currents, with 20 A having the highest impact on the oscillations in simulations and 15 A having the highest impact in experimental verification. On the switching energy, the gate inductance was not shown to have a significant impact on switching losses while the gate resistance had a much more significant impact on the switching losses. / Kiselkarbid som halvledare med brett bandgap har flera fysiska och elektriska fördelar jämfört med kisel för högspännings- och högfrekvensapplikationer. SiC som en MOSFET-enhet har många fantastiska egenskaper som lägre resistans och låga ingångskapacitanser. Men på grund av dess höga omkopplingsförmåga upplever SiC MOSFET-baserade omvandlarkretsar högre dv/dt och di/dt transienter och är därför mer mottagliga för parasitiska element. Denna avhandling undersöker interaktionen mellan gate-drivkretsens parasitära induktans och resistans på kopplingsbeteendet på SiC DMOSFET (plan) och UMOSFET (trench). För att undersöka detta användes en dubbelpulstest (DPT) mätuppställning både i simulering och experimentellt. Inverkan av grindinduktansen och motståndet på svängningsbeteendet i VGS under Millerperioden visade sig vara beroende av den övre anordningens tillstånd. Vidare upptäcktes att den övre anordningen hade en hög inverkan på svängningarna i VGS via dess parasitiska induktans. Gate-induktansen visade en blandad inverkan på IDS- och VDS-översvängning, med IDS-översvängning som minskade med ökande gateinduktans och det omvända fallet för VDS. Gatemotståndet visade dock en konsekvent inverkan på både IDS- och VDS-överskridningar, med båda minskande med ökande gatemotstånd. Dessa resultat pekar slutligen på inverkan av di/dt- och dv/dt-transienter. Ett intressant resultat som observerats på dessa grundorsaker visade att i det använda DPT-arrangemanget kan lägre testströmnivåer ha mer signifikant inverkan på svängningarna i VGS än högre testström vid variation av testströmmarna, med 20 A som har den högsta inverkan på svängningarna i simuleringar och 15 A som har störst effekt vid experimentell verifiering. På omkopplingsenergin visades inte grindinduktansen ha någon signifikant inverkan på omkopplingsförlusterna medan grindresistansen hade mycket mer betydande inverkan på omkopplingsförlusterna.