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Microprocessor systems have been advancing at a phenomenal rate, with each new generation introducing improved fabrication processes and architectural innovations. Unfortunately, traditional fabrication techniques cannot sustain this exponential growth indefinitely. Thus, additional research into conventional design methodologies, such as those involving asynchronous design techniques, is essential to maintain the current trend. The primary objective of this research was to explore the viability of asynchronous design techniques as an alternative to current synchronous design methods. In order to simulate the design complexities involved in a real-world system, the MIPS-II R2000 pipelined microprocessor was selected as the basis for comparison. All of the experimental processors were designed in VHDL on an FPGA using the Altera Quartus II design package. The processors were tested using timing simulations with various benchmarks to determine the advantages and disadvantages of each design technique. Four distinct asynchronous processors with varying handshaking and synchronization methods were designed and compared to the baseline synchronous processor. Although, in theory, each of the asynchronous design variations had its merits, it was clear that not all of them were well suited for practical use in a large-scale microprocessor environment. Three of the asynchronous processors suffered from an excessive amount of synchronization overhead that drastically reduced their overall system performance to the point where they performed considerably worse than the baseline synchronous processor. However, one asynchronous processor performed considerably better: with only a 1.5 percent increase in logic complexity, it outperformed the baseline synchronous processor by over 10 percent on a sorting test benchmark and had a maximum theoretical speedup of over 36 percent. Therefore, it is evident that asynchronous designs have the potential to improve the performance of traditional synchronous systems. However, designing efficient and hazard-free asynchronous logic on an FPGA proved to be challenging and time-consuming. With additional research and further design tool improvements to facilitate the creation of optimized glitch-free logic, asynchronous design methodologies may become a viable alternative to traditional synchronous designs and contribute to the current trend of microprocessor advancement. / Thesis (Master, Electrical & Computer Engineering) -- Queen's University, 2007-12-19 01:30:22.248

This thesis presents the results of research performed into the simulation of electrical power systems using a set of microprocessors operating in parallel , The uses and methods of simulation on analog and single processor computers are discussed as well as on multiple processor machines . It then considers various methods already used in the field of simulation for both the dynamic and network sets of equations in detail and the problems of using them on parallel processors . Several possible methods of parallel simulation are proposed and the best of these developed into a detailed algorithm for simulating both the dynamic and network portions of the power system .The different types of multiprocessor system are looked at , both in terms of physical configuration and the type of hardware used to implement the different types of system .The problems inherent in parallel computing are discussed and a form of multiprocessor, suitable for the simulation algorithm, is then developed taking these problems Into account. The hardware is developed using widely available hardware and the algorithm Is then Implemented upon this hardware .The results obtained using the simulator show that the proposed system provides a more economical solution, both in terms of the time taken in producing results and in the cost of the system, when compared with a conventional single processor computing system such as a mini computer.

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