L'objectif de mon travail est de comprendre le rôle de Rrp6, une exoribonuclease 3'-5', dans l'expression des gènes. Dans ce but, j'ai utilisé le promoteur du virus de l'immunodéficience humaine (VIH-1) comme modèle d'étude de la régulation des gènes chez les mammifères. En utilisant ce modèle dans le chapitre 1 des résultats, nous avons montré l'existence d'un nouveau mécanisme de répression de l'expression des gènes dépendant de l'ARN qui requiert les actions combinées de Rrp6 et du microprocesseur. A la suite de ce travail, nous avons caractérisé les complexes de protéines associés à Rrp6 qui contribuent à cette répression de la transcription (résultats - chapitre 2). Ces deux études suggèrent un rôle de Rrp6 dans la répression de la transcription au niveau du promoteur du VIH-1 mais aussi sur certains gènes cellulaires. Au cours des études présentées dans le chapitre 1, nous avons observé une forte diminution de l'expression de la protéine Dicer dans les cellules déplétées de Rrp6. Dicer est un élément central de la régulation de la maturation des microARN (miRNA) et donc joue un rôle important dans tous les processus cellulaires qui sont régulés par les miRNA, incluant de nombreux processus biologiques et physiologiques. Ainsi, il est important de connaitre les voies de régulation de Dicer. Dans le chapitre 3 des résultats, nous décrivons un nouveau mécanisme de régulation de Dicer par Rrp6. En effet, nos résultats montrent que Rrp6 est nécessaire pour un epissage efficace de l'ARNm de Dicer. Nos travaux décrivent un nouveau role de Rrp6 dans des processus cellulaires distincts: transcription et splicing / The objective of my doctoral work was to understand the role of a 3' to 5' exoribonuclease, Rrp6, in gene expression. I used the Human Immunodeficiency Virus (HIV-1) promoter as a model to study gene regulation in mammalian cells. Using this model, in Result-chapter 1, we demonstrated a novel mechanism of RNA-dependent transcriptional gene silencing that depends on the cooperative activities of Rrp6 and microprocessor. Following this study, we characterized the Rrp6-containing complex that contributes to the transcriptional silencing at HIV-1 promoter (Result-chapter 2). These two studies suggest a role for Rrp6 in transcriptional repression at the HIV-1 promoter and also at a subset of cellular genes. During the course of our studies presented in chapter 1, we observed a dramatic decrease of Dicer protein level in the cells depleted of Rrp6. Dicer is a central regulator of microRNA (miRNA) maturation and therefore exerts an important role in all cellular processes that are regulated by miRNAs, including diverse biological and physiological processes. Thus, it is important to know how Human Dicer1 is regulated. In Result-chapter 3, we describe a new regulatory mechanism of Dicer1 expression by Rrp6. Indeed, our results demonstrate that Rrp6 is required for efficient splicing of Dicer1 mRNA. Our work describes a novel role for Rrp6 in distinct cellular processes: transcription and splicing.

by Lai Kin-wing. / Typescript (photocopy) / Includes bibliographical references / Thesis (M.Ph.)--Chinese University of Hong Kong, 1982

<p>Detta examensarbete är framtaget av SSAB:s ingenjörer i fabriken SSAB Oxelösund. Uppdraget består i att konstruera en ny hård- och mjukvara för en befintlig valsningsklocka.</p><p>Examensarbetet består av flera delar, där den första delen är att konstruera och välja komponenter till en prototyp av ny hårdvara till klockan. När delarna är valda kommer dem att testas med ett laborationskort med den valda processorn för att utvärdera att delarna är kompatibla innan den slutliga hårdvaran beställs.</p><p>Den andra består i att programmera mjukvara till processorn som kommer att vara kärnan till klockan. Processorn kommer att styra samt beräkna alla in- och utsignaler till alla komponenter som finns i klockan.</p><p>Den tredje och avslutande delen består av konstruera den slutgiltiga produkten med hjälp av CAD-verktyg. En layout med alla valda komponenter produceras.</p><p>Tanken med projektet är att man ska uppdatera äldre komponenter till nyare som är lättillgängligare att införskaffa. Det ska vara lättare att felsöka med hjälp av en enkel meny genom att ansluta kortet mot en dator. Man ska kunna använda samma mjuk- och hårdvara oavsett vilken av de två klocktyper som används.</p><p>Jag har fått olika resultat av skapandet av det nya prototypskortet. Det har varit mycket laborerande att hitta komponenter till hårdvaran för att få en fungerande prototyp till klockorna. Programmeringen av mjukvaran har varit lite varierande beroende på vilken A/D-omvandlare som har använts. I övrigt har de mesta arbetet gått åt att skapa en väl fungerande meny som ska fungera för båda klockorna. Tillverkning av en slutversion av prototypen är beställd men inte levererad. Programmeringen av Ethernet-kontrollen har inte hunnits med.</p><p>Fördelarna med det nya systemet är att det är lättare att hitta ersättningskomponenter vid reparation samt att menystyrd felsökning är snabb och enkel. Till exempel kan man med menystyrd felsökning se om A/D-omvandlarna får något värde eller om det är dålig anslutning mellan komponenterna. Med det nya systemet är det också möjligt att implementera ny mjukvara.</p> / <p>This thesis has been developed by SSAB´s engineers in the fabric SSAB Oxelösund. The assignment is to design a new hardware and software for a roller clock.</p><p>The thesis has several parts, where the first part is to construct and choose components to a prototype of the hardware to the watch. When the parts are chosen, they will be tested with an elaboration card with the chosen processor to be evaluated that the parts are compatible before the final hardware is ordered.</p><p>The second part is to program software for the processor that will be the core for the watch. The processor will be controlling and calculate all in signals and out signals to all components there is in the watch.</p><p>The third and the ending part are to construct the final product with help of CAD tools. A layout with all the chosen components produced.</p><p>The thought with the project is to update older components to newer ones that are more easily accessible to get. It shall be easier to debug with help of one simple menu by connecting the card against a computer. It will be able to use the same software and hardware to any kind of the two clock types that is in use.</p><p>I have got different results by creating the new prototype card. It has been a lot of elaborations to find the components to the hardware to get a functional prototype for the watches. Programming of the software has been a bit varying depending on what kind of A/D-converter has been used. Otherwise the most work of programming has been to create a functional menu that is functional for the both watches. The production of the final product of the prototype has been ordered but not yet delivered. Programming of the Ethernet control has not yet been managed.</p><p>The advantages with the new systems are it´s easier to get replacement parts at reparation and with the menu controlled error seeking it gets easier and quicker to find the errors. For an example it's possible with menu controlling to see if the A/D-converters gets any values or if there is bad connections between the components. With the new system it is also possible to implement new software.</p>

Two problems of computer security are investigated. On one hand, we are facing a practical problematic of actual processors: the cache, an element of the architecture that brings flexibility and allows efficient utilization of the resources, is demonstrated to open security breaches from which secret information can be extracted. This issue required a delicate study to understand the problem and the role of the incriminated elements, to discover the potential of the attacks and find effective countermeasures. Because of the intricate behavior of a processor and limited resources of the cache, it is extremely hard to write constant-time software. This is particularly true with cryptographic applications that often rely on large precomputed data and pseudo-random accesses. The principle of time-driven attacks is to analyze the overall execution time of a cryptographic process and extract timing profiles. We show that in the case of AES those profiles are dependent on the memory lookups, i.e. the addition of the plaintext and the secret key. Correlations between some profiles with known inputs and some with partially unknown ones (known plaintext but unknown secret key) lead to the recovery of the secret key. We then detail access-driven attacks: another kind of cache-based side channel. This case relies on stronger assumptions regarding the attacker's capacities: he must be able to run another process, concurrent to the security process. Even if the security policies prevent the so-called "spy" process from accessing directly the data of the "crypto" process, the cache is shared between them and its behavior can lead the spy process to deduce the secrets of the crypto process. Several ways are explored for mitigations, depending on the security level to reach and on the attacker's capabilities. The respective performances of the mitigations are given. The scope is however oriented toward software mitigations as they can be directly applied to patch programs and reduce the cache leakage. On the other hand, we tackle a situation of computer science that also concerns many people and where important economical aspects are at stake: although spam is often considered as the other side of the Internet coin, we believe that it can be defeated and avoided. A increasing number of researches for example explores the ways cryptographic techniques can prevent spams from being spread. We concentrated on studying the behavior of the spammers to understand how e-mail addresses can be prevented from being gathered. The motivation for this work was to produce and make available quantitative results to efficiently prevent spam, as well as to provide a better understanding of the behavior of spammers. Even if orthogonal, both parts tackle practical problems and their results can be directly applied.

No description available.

Detta examensarbete är framtaget av SSAB:s ingenjörer i fabriken SSAB Oxelösund. Uppdraget består i att konstruera en ny hård- och mjukvara för en befintlig valsningsklocka. Examensarbetet består av flera delar, där den första delen är att konstruera och välja komponenter till en prototyp av ny hårdvara till klockan. När delarna är valda kommer dem att testas med ett laborationskort med den valda processorn för att utvärdera att delarna är kompatibla innan den slutliga hårdvaran beställs. Den andra består i att programmera mjukvara till processorn som kommer att vara kärnan till klockan. Processorn kommer att styra samt beräkna alla in- och utsignaler till alla komponenter som finns i klockan. Den tredje och avslutande delen består av konstruera den slutgiltiga produkten med hjälp av CAD-verktyg. En layout med alla valda komponenter produceras. Tanken med projektet är att man ska uppdatera äldre komponenter till nyare som är lättillgängligare att införskaffa. Det ska vara lättare att felsöka med hjälp av en enkel meny genom att ansluta kortet mot en dator. Man ska kunna använda samma mjuk- och hårdvara oavsett vilken av de två klocktyper som används. Jag har fått olika resultat av skapandet av det nya prototypskortet. Det har varit mycket laborerande att hitta komponenter till hårdvaran för att få en fungerande prototyp till klockorna. Programmeringen av mjukvaran har varit lite varierande beroende på vilken A/D-omvandlare som har använts. I övrigt har de mesta arbetet gått åt att skapa en väl fungerande meny som ska fungera för båda klockorna. Tillverkning av en slutversion av prototypen är beställd men inte levererad. Programmeringen av Ethernet-kontrollen har inte hunnits med. Fördelarna med det nya systemet är att det är lättare att hitta ersättningskomponenter vid reparation samt att menystyrd felsökning är snabb och enkel. Till exempel kan man med menystyrd felsökning se om A/D-omvandlarna får något värde eller om det är dålig anslutning mellan komponenterna. Med det nya systemet är det också möjligt att implementera ny mjukvara. / This thesis has been developed by SSAB´s engineers in the fabric SSAB Oxelösund. The assignment is to design a new hardware and software for a roller clock. The thesis has several parts, where the first part is to construct and choose components to a prototype of the hardware to the watch. When the parts are chosen, they will be tested with an elaboration card with the chosen processor to be evaluated that the parts are compatible before the final hardware is ordered. The second part is to program software for the processor that will be the core for the watch. The processor will be controlling and calculate all in signals and out signals to all components there is in the watch. The third and the ending part are to construct the final product with help of CAD tools. A layout with all the chosen components produced. The thought with the project is to update older components to newer ones that are more easily accessible to get. It shall be easier to debug with help of one simple menu by connecting the card against a computer. It will be able to use the same software and hardware to any kind of the two clock types that is in use. I have got different results by creating the new prototype card. It has been a lot of elaborations to find the components to the hardware to get a functional prototype for the watches. Programming of the software has been a bit varying depending on what kind of A/D-converter has been used. Otherwise the most work of programming has been to create a functional menu that is functional for the both watches. The production of the final product of the prototype has been ordered but not yet delivered. Programming of the Ethernet control has not yet been managed. The advantages with the new systems are it´s easier to get replacement parts at reparation and with the menu controlled error seeking it gets easier and quicker to find the errors. For an example it's possible with menu controlling to see if the A/D-converters gets any values or if there is bad connections between the components. With the new system it is also possible to implement new software.

Today, more and more embedded hardware devices are reaching the market and consumers with a demand for smaller and better devices than yesterday. Increasing the performance of a device decreases the operating time since more power is consumed, still, decreasing the size of the device also decreases operating time as the battery size decreases.To allow the performance to increase and the size of the device to decrease, the designer must nd techniques allowing the hardware to consume less power during normal usage of a device than during the peak usage.In this thesis an implementation of an ARM based microprocessor system is presented and used for measuring and evaluation of the power consumption possibilities of the system.

This report deals with the modeling of a part of the communication system based on the IEEE 802.11a standard which represents the next generation of wireless LAN with greater scalability, better interference immunity and significantly higher speed, up to 54 Mbps. 802.11a uses Orthogonal Frequency Division Multiplexing (OFDM) where modulation is performed by an IFFT and the demodulation by an FFT. After modeling the FFT in Matlab and C, the FFT implementation has been validated using a soft microprocessor core by Xilinx (Microblaze) and the results were compared.

With the advanced of the technique, we can design more IP in the same area space chip. The embedded system has more powerful about its application. We need to have a more efficient core processor to support the whole embedded system in complex system environment. The main purpose of this paper is increased the calculated speed, memory management and debugging for SYS32TME III, which is designed by our lab as an ARM10 like processor. We integrate the cache/MMU and EICE( Embedded in-circuit emulator ) into the embedded processor core. Using the cache/MMU, we can not only speed up the processor which access external memory time but also use the virtual address for Operating System. In order to keep the correctness of the system and speed up the system integration time, we use five functional (cache off, cache on and MMU off with cache hit/miss, cache on and MMU on with cach hit/cache miss and TLB hit/cache miss and TLB miss) tests to verify the cache/MMU and six coprocessor instructions (LDC, MCR, MCRR, MRC, MRRC, STC ) to verify the EICE. After that, we also use the regression test about the microprocessor, cache/MMU and EICE system integration. In the end, we turned the performance about the integrated cache/MMU and EICE, so that we can support an 200MHz ARM 10-like processor by 0.18£gm.

In embedded system, the system resource is limited. So, small is the most important feature of the embedded system. In this thesis, we propose a fast way to design a 16-bit microprocessor through reducing the 32-bit RISC CPU based on ARM 4vT Instruction set to the 16-bit RISC Thumb microprocessor. And through building the programming model, we can reach to save the design time of developing the compiler and assembler to keep its software environment.