Powered prostheses are at the forefront of prosthetic technology, improving functionality by providing positive power to joints in the absence of native anatomy. Currently, there is no commercially available powered solution for hip-level amputees, and most hip prostheses are mounted to the front of the prosthetic socket. This thesis designed, fabricated, and tested a novel Laterally Mounted Powered Hip Joint (LMPHJ) that augments user gait to promote improved walking patterns. The LMPHJ attaches to the lateral side of the prosthetic socket, locating the hip centre of rotation closer to the anatomical location while ensuring user safety and stability. The new design locates the motor and all electronics in the thigh area, thereby maintaining a low profile while transmitting the required hip moments to the joint centre of rotation. A prototype was designed and manufactured to evaluate LMPHJ performance. Mechanical testing followed the ISO 15032:2000 standard and successfully demonstrated the joint's resistance to everyday loading conditions. Functional testing involved integrating the LMPHJ, Ossur Rheo Knee, and Ossur Pro-Flex XC with a prosthesis simulator that allowed three able-bodied participants to walk with the powered prosthesis successfully. This validated the mechanical design for walking over level ground and demonstrated that the LMPHJ is ready for next phase evaluation with hip disarticulation amputee participants.

<p> In the past, analog circuits, discrete digital logic circuits or minicomputers have been used to implement the signal processing section of a sonar systems. More recently, microprocessor based logic circuit designs have produced a new breed of system design approach which gives designers the flexibility that has never been available through the use of analog or discrete logic circuits; however, due to the inherent slow speed of the metal-oxide semiconductor (MOS) logic circuits, incorporating microprocessors in the implementation of a sonar signal processor is not feasible. With the advent of bipolar Schottky large scale integrated circuit technology, the speed performance of the microprocessors have been improved considerably, and signal processor designs employing microprocessors are now feasible. </p> <p> The main objective of this work is to design, implement, and test a real-time digital sonar signal processor for processing pulsed CW signals. With design based on the use of the bit slice microprocessor, a signal processor has been constructed that has an 8 bit input, a 16 bit output. The processor is capable of detecting 16 different Doppler shifts. Laboratory generated signals are used in the testing and the experimental results show good agreement with the theory. A possible means of expanding the existing single channel signal processor into a multichannel processor has also been outlined. </p> / Thesis / Master of Engineering (MEngr)

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Power line communications (PLC) has been considered by utility companies for over a half century and for home networking in recent years. However, PLC at the IC level, or even at the PCB level, has not been investigated outside Dr. Ha's research group. This thesis investigates the feasibility of PLC over power distribution networks (PDNs) of advanced microprocessors. A PDN in an integrated circuit (IC) is ubiquitous as seen by the internal logic, i.e., a power line is accessible to any internal node. This suggests the possibility of monitoring or controlling the logic value of any internal node through a power line by attaching a simple sensing/control circuit to the node. Routing the data through a power line avoids the necessity of preplanning the routing of a data path between the node and an external data pin. PLC over microprocessor PDNs also provide a viable means for "run-time testing" as well as for monitoring the so called "large time-constant errors" resulting from aging and temperature variations. In this thesis, we considered impulse-based ultra wideband (I-UWB) communication technology for PLC over PDNs of microprocessors. I-UWB has several advantages for PLC over PDNs due to its robustness to multipath effects, simple hardware for transmission and reception of pulses and, more importantly, reduced interference to the normal operation of microprocessors. A microprocessor PDN is heavily decoupled to damp the resonances in the power supply impedance as well as to reduce the slew rate of current variations by locally supplying (sinking) currents to (from) the switching nodes. Consequently, a PDN behaves like a bulky lowpass filter for high frequency signals. However, the inductance component of decoupling capacitors becomes more significant beyond the self resonant frequency (SRF) of the capacitors. So, a PDN becomes essentially a distributed circuit beyond the SRF and is no longer a lowpass filter. Indeed, high frequency PDN models developed earlier at Dr. Ha's group show that there exist multiple frequency bands where high frequency signals can propagate through the PDN with relatively low attenuation [3] [4]. The major contributions of our research lie in three areas. First, we verified existence of passbands on PDN's transfer characteristics through measurements. We carried out high frequency measurements on the PDN of Intel's 65 nm Pentium processor and 45 nm Core 2 Duo processor. We measured PDN transfer characteristics up to several GHz from a core power pin on a tester board to an on-chip power node for both active and cold microprocessor dies. The measurements show the existence of narrow, sporadic and migratory passbands i.e. location of passbands change from one generation of processor to the next. The migratory nature of passbands requires the I-UWB receiver and a transmitter to cover a wide range of frequencies rather than a specific passband. Second, we have developed a PDN communication channel model for system level study. To develop the channel model, we also performed noise measurements on Intel microprocessors. The link budget was calculated based on the channel model and appropriate modulation schemes were suggested through the system level study. Third, we investigated design of an I-UWB receiver and a transmitter, which cover a wide bandwidth. The proposed receiver and transmitter designs were evaluated through simulations in TSMC 0.18 μm CMOS process. Our simulation indicates that the PLC over a PDN is feasible with a relatively simple digital-process friendly I-UWB receiver and a transmitter. / Ph. D.

Power line communications (PLC) as applied to electrical power grid is known since long; however, PLC in microprocessors was recently introduced by VTVT Lab. Since power distribution network (PDN) inside a microprocessor is ubiquitous, therefore, any node inside a microprocessor can be accessed by attaching a simple communication circuit to it. The scheme is extremely attractive as it avoids the routing overhead of the data-path between an internal node and an I/O pin. A number of applications are possible for PLC in microprocessors such as on-line testing, monitoring/control of internal nodes, fault diagnosis etc. Feasibility of the PLC approach has been extensively studied by earlier researchers at VTVT. The feasibility studies investigated the frequency response of a microprocessor's PDN and looked for existence of passbands — frequency bands where signal attenuation through the PDN is small. Two different approaches were followed—the first approach employed analytical modeling of the high frequency characteristics of the PDN, while the second approach conducted measurements on Intel® microprocessors' PDN. Although, differences were observed in the results of the two approaches; both the approaches demonstrated existence of passbands, thus affirming the feasibility of the PLC scheme. This thesis presents a system level study conducted to estimate performance of the PLC scheme. Measurement results were used to model the PDN channel. The study provides useful insights for the design of microprocessor level PLC system. Specifically, the study estimates optimal pulse width required to maximize the system performance and the range of achievable data-rates. The study demonstrates that it is feasible to communicate data through a microprocessor's PDN without inducing large disturbances on the power line. The other work presented in this thesis is the design of low power receiver for microprocessor level PLC, also called data recovery block. The proposed design of data recovery block employs Correlation Detection (CD) receiver architecture. The design has been implemented in IBM 0.13 µm CMOS process and has been verified to operate reliably across Process, Voltage and Temperature variations. The design has a small foot-print of 300 µm x 160 µm and consumes 3.58 mW while operating from 1.2 V power supply. / Master of Science