<p>This thesis presents a five-transistor SRAM intended for the advanced microprocessor cache market. The goal is to reduce the area of the cache memory array while maintaining competitive performance. Various existing technologies are briefly discussed with their strengths and weaknesses. The design metrics for the five-transistor cell are discussed in detail and performance and stability are evaluated. Finally a comparison is done between a 128Kb memory of an existing six-transistor technology and the proposed technology. The comparisons include area, performance and stability of the memories. It is shown that the area of the memory array can be reduced by 23% while maintaining comparable performance. The new cell also has 43% lower total leakage current. As a trade-off for these advantages some of the stability margin is lost but the cell is still stable in all process corners. The performance and stability has been validated through post-layout simulations using Cadence Spectre.</p>

<p>The DMA(direct memory access) controller is a special component in DSP processor used to offload the data transferring from CPU and improve the data access efficiency in the microprocessor.</p><p>This paper describes the design and implementation of DMA(direct memory access) device for microprocessor developed using C++ Language and SystemC libraries. The main facts covered within this report are the structure of a microprocessor with embedded DMA, and some interesting points of SystemC and TLM library that are useful for the design and implementation of the system level design.</p><p>This paper starts with an introduction of the theory of DMA , the structure of the microprocessor and the multicore microprocessor. Next it goes further into the DMA specification discussion. The next chapter is the implementation of DMA and the microsystem, later on in this chapter is an explanation of the SystemC methods I used in the system design.</p><p>At last, the simulation results of the whole system is presented and analyzed. The utility of the DMA is discussed and calculated.</p><p>With all these aspects covered in the paper, it is easy for the readers to understand the DMA theory , micro architecture as well as the fundamental knowledge of SystemC.</p>

A novel hybrid cooling scheme is proposed to remove non-uniform heat flux in real time from the microprocessor. It consists of a liquid cooled microchannel heat sink to remove the lower background heat flux and superlattice coolers to dissipate the high heat flux present at the hotspots. Superlattice coolers (SLC) are solid-state devices, which work on thermoelectric effect, and provide localized cooling for hotspots. SLCs offer some unique advantage over conventional cooling solutions. They are CMOS compatible and can be easily fabricated in any shape or size. They are more reliable as they don't contain any moving parts. They can remove high heat flux from localized regions and provide faster time response. Experimental devices are fabricated to characterize the steady-state, as well as transient performance, of the hybrid cooling scheme. Performance of the hybrid cooling scheme has been examined under various operating conditions. Effects of various geometric parameters have also been thoroughly studied. Heat flux in excess of 300 W/cm² has been successfully dissipated from localized hotspots. Maximum cooling at the hotspot is observed to be more than 6 K. Parasitic heat transfer to the superlattice cooler drastically affects its performance. Thermal resistance between ground electrode and heat sink, as well as thermal resistance between ground electrode and superlattice cooler, affect the parasitic heat transfer from to the superlattice cooler. Two different test devices are fabricated specifically to examine the effect of both thermal resistances. An electro-thermal model is developed to study the thermal coupling between two superlattice coolers. Thermal coupling significantly affects the performance of an array of superlattice coolers. Several operating parameters (activation current, location of ground electrode, choice of working fluid) affect thermal coupling between superlattice coolers, which has been computationally as well as experimentally studied. Transient response of the superlattice cooler has also been examined through experiments and computational modeling. Response time of the superlattice cooler has been reported to be less than 35 µs.

This thesis presents a five-transistor SRAM intended for the advanced microprocessor cache market. The goal is to reduce the area of the cache memory array while maintaining competitive performance. Various existing technologies are briefly discussed with their strengths and weaknesses. The design metrics for the five-transistor cell are discussed in detail and performance and stability are evaluated. Finally a comparison is done between a 128Kb memory of an existing six-transistor technology and the proposed technology. The comparisons include area, performance and stability of the memories. It is shown that the area of the memory array can be reduced by 23% while maintaining comparable performance. The new cell also has 43% lower total leakage current. As a trade-off for these advantages some of the stability margin is lost but the cell is still stable in all process corners. The performance and stability has been validated through post-layout simulations using Cadence Spectre.

The DMA(direct memory access) controller is a special component in DSP processor used to offload the data transferring from CPU and improve the data access efficiency in the microprocessor. This paper describes the design and implementation of DMA(direct memory access) device for microprocessor developed using C++ Language and SystemC libraries. The main facts covered within this report are the structure of a microprocessor with embedded DMA, and some interesting points of SystemC and TLM library that are useful for the design and implementation of the system level design. This paper starts with an introduction of the theory of DMA , the structure of the microprocessor and the multicore microprocessor. Next it goes further into the DMA specification discussion. The next chapter is the implementation of DMA and the microsystem, later on in this chapter is an explanation of the SystemC methods I used in the system design. At last, the simulation results of the whole system is presented and analyzed. The utility of the DMA is discussed and calculated. With all these aspects covered in the paper, it is easy for the readers to understand the DMA theory , micro architecture as well as the fundamental knowledge of SystemC.

Functional verification is a critical problem facing the semiconductor industry: hardware designs are extremely complex and highly optimized, and even a single bug in deployed systems can cost more than $10 billion. We focus on the verification of pipelining, a key optimization that appears extensively in hardware systems such as microprocessors, multicore systems, and cache coherence protocols. Existing techniques for verifying pipelined machines either consume excessive amounts of time, effort, and resources, or are not applicable at the bit-level, the level of abstraction at which commercial systems are designed and functionally verified. We present a highly automated, efficient, compositional, and scalable refinement-based approach for the verification of bit-level pipelined machines. Our contributions include: (1) A complete compositional reasoning framework based on refinement. Our notion of refinement guarantees that pipelined machines satisfy the same safety and liveness properties as their instruction set architectures. In addition, our compositional framework can be used to decompose correctness proofs into smaller, more manageable pieces, leading to drastic reductions in verification times and a high-degree of scalability. (2) The development of ACL2-SMT, a verification system that integrates the popular ACL2 theorem prover (winner of the 2005 ACM Software System Award) with decision procedures. ACL2-SMT allows us to seamlessly take advantage of the two main approaches to hardware verification: theorem proving and decision procedures. (3) A proof methodology based on our compositional reasoning framework and ACL2-SMT that allows us to reduce the bit-level verification problem to a sequence of highly automated proof steps. (4) A collection of general-purpose refinement maps, functions that relate pipelined machine states to instruction set architecture states. These refinement maps provide more flexibility and lead to increased verification efficiency. The effectiveness of our approach is demonstrated by verifying various pipelined machine models, including a bit-level, Intel XScale inspired processor that implements 593 instructions and includes features such as branch prediction, precise exceptions, and predicated instruction execution.

Embedded in circuit emulator (EICE) is the most common and widely used debugging techniques for microprocessors. Because the ICE is capable to provide diverse debugging and testing mechanisms, such as: single-step debugging, breakpoints setting and detection, monitoring, and modification of internal resources. However, the shortcoming of the conventional embedded in circuit emulator (EICE) is that the operation of the processor has to be suspended during debugging, which is categorized as static debugging (Static Debug) and is infeasible for real-time debugging. Therefore, this paper proposes a design alternative to support the real-time system debugging without suspending the microprocessor via the debug hardware Coprocessor14 (the Debug Coprocessor). In this paper, the embedded in circuit emulator is combined with Coprocessor 14 to provide both the static debugging and Run-time system debugging. After incorporating CP14 with the debugging mechanism, the control of the debug hardware is no longer limited to use the IEEE 1149.1 test port during debugging. On the other hand, the set of debugging constraints and the observation of the internal state of the microprocessor can be achieved by inserting the Coprocessor instruction at the program level.

For improving the performance and application of microprocessor, it is necessary to integrate pipelined core, exception control unit, cache unit and memory management unit (MMU). The operating system is an effective way for microprocessor integration verification. However, it is not a feasible debugging methodology to detect the exact design bug while operating system booting crash. We found the main execution features of operating system are the data transfer and exception handling. We propose an integration verification methodology based on these execution features. The methodology is to verify concurrent cache transfer operation, consecutive cache transfer operation, external interrupt exception handling, page fault exception handling and multiple interrupt exception handling for microprocessor integration. We utilize ARM7-Like developed by our laboratory to do the experiment. It is effective to detect the design bugs in RTL simulation by the software-based verification methodology proposed by us. The modified ARM7-Like microprocessor is able to successfully boot Linux kernel and execute user applications in FPGA.

<p>Embedded microcomputers are used in a wide range of applications nowadays. Avionics is one of these areas and requires extra attention regarding reliability and determinism. Thus, these issues should also be born in mind in addition to performance when evaluating embedded microcomputers.</p><p>This master thesis suggests a framework for performance evaluation of two members of the PowerPC microprocessor family, namely the MPC5554 from Freescale and PPC440EPx from AMCC, and analyzes the results within and between these processors. The framework can be generalized to be used in any microprocessor family, if required.</p><p>Apart from performance evaluation, this thesis also suggests also a new terminology by introducing the concept of determinism levels to be able to estimate determinism issues in avionics applications more clearly, which is crucial regarding the requirements and working conditions of this very application. Such estimation does not include any practical results as in performance evaluation, but rather remains theoretical. Similar to Automark™ used by AutoBench™ in the EEMBC Benchmark Suite, we introduce a new performance metric score that we call ”Aviomark” and we carry out a detailed comparison of Aviomark with the traditional Automark™ score to be able to see how Aviomark differs from Automark™ in behavior.</p><p>Finally, we have developed a graphical user interface (GUI) which works in parallel with the Green Hills MULTI Integrated Development Environment (IDE) in order to simplify and automate the evaluation process. By the help of the GUI, the users will be able to easily evaluate their specific PowerPC processors by starting the debugging from MULTI IDE.</p>

Main memory system performance is crucial for high performance microprocessors. Even though the peak bandwidth of main memory systems has increased through improvements in the microarchitecture of Dynamic Random Access Memory (DRAM) chips, conventional on-chip memory systems of microprocessors do not fully take advantage of it. This results in underutilization of the DRAM system, in other words, many idle cycles on the DRAM data bus. The main reason for this is that conventional on-chip memory system designs do not fully take into account important DRAM characteristics. Therefore, the high bandwidth of DRAM-based main memory systems cannot be realized and exploited by the processor. This dissertation identifies three major performance-related characteristics that can significantly affect DRAM performance and makes a case for DRAM characteristic-aware on-chip memory system design. We show that on-chip memory resource management policies (such as prefetching, buffer, and cache policies) that are aware of these DRAM characteristics can significantly enhance entire system performance. The key idea of the proposed mechanisms is to send out to the DRAM system useful memory requests that can be serviced with low latency or in parallel with other requests rather than requests that are serviced with high latency or serially. Our evaluations demonstrate that each of the proposed DRAM-aware mechanisms significantly improves performance by increasing DRAM utilization for useful data. We also show that when employed together, the performance benefit of each mechanism is achieved additively: they work synergistically and significantly improve the overall system performance of both single-core and Chip MultiProcessor (CMP) systems. / text