Uppdragsgivaren Saab Electronic Defence Systems i Jönköping erbjuder ett flertal produkter främst inom avioniksystem. För att kunna utvärdera och kontrollera produktens design i ett tidigt skede så kan en simulering av systemets beteende och att felsöka så tidigt som möjligt vara ett möjligt alternativ. En systemsimulering kan innebära att mjukvaruutveckling och felsökning kan påbörjas långt innan hårdvaruprototypen är tillgänglig, med samma storlek och komplexitet som systemet. Andra fördelar med simulering är att det går enklare att fastställa orsaken till systemkrasch, hitta de längsta exekveringstiderna och göra felinjiceringar. Syftet med detta examensarbete är att testa och utvärdera hur simulatorer och emulatorer är som utvecklings- och testverktyg. Rapporten innehåller en marknadsundersökning där tio stycken emulatorer och simulatorer hittades. Av dessa valdes två stycken ut, Wind River Simics och Imperas OVPSim. Tester utfördes för användarvänlighet, debugging, samt jämförande tester mellan riktig hårdvara och simulerad miljö. Resultatet visar att simulatorer kan hjälpa till vid produktutveckling, men att de ännu inte är så optimala för att utvärdera hårdvara i. Detta för att avvikelser kan förekomma i exekveringstider mellan riktig och simulerad hårdvaruarkitektur. / This thesis has been carried out in cooperation with Saab Electronic Defence Systems in Jönköping which has a wide range of products, mainly for Avionic applications. In order to evaluate and verify their design it is often required to simulate behaviour and debug as early as possible. System simulation can enable software development and debug to commence long before a hardware prototype is available and also scale with the size and complexity of the system. Another benefit of simulation is to more easily determine root causes to system crashes, establish worst case execution time cases and making fault injection. Therefore this thesis will focus on evaluating simulators and emulators, as development- and testing tools. This report contains a marketing research, where ten emulators and simulators were found. Of these, two simulators were chosen for further investigation; WindRiver Simics and Imperas OVPSim. The evaluations considered both usability and debugging features as well as comparative tests between real hardware and the simulated environment. The results show that simulators can help in product development, but they are not yet optimal for evaluating hardware. This is because deviations may occur in execution times between real and simulated hardware architectures.

Examensarbetsuppgiften har gått ut på att genomföra en prestandajämförelse mellan en hård och en mjuk processorkärna integrerad i en FPGA, i detta fall, en Virtex4 FX12 från Xilinx. System med de olika kärnorna har tagits fram, där antalet klockcykler för att genomföra olika beräkningar har mäts. Bland annat har algoritmen Fast Fourier Transform och dess invers beräknats för en vektor. De kärnor som har provats är den mjuka MicroBlaze framtagen av Xilinx samt den hårda PowerPC 405. Prestandan för systemet med mjuk kärna var 65 % av det med hård kärna Förutom prestandamätningarna har en vidare teoretisk jämförelse mellan kärnorna genomförts. Utifrån den har slutsatsen dragits att när man behöver små volymer av FPGA-kretsar eller flera olika beräkningar skall göras är FPGAer med hård kärna att föredra. Om det är större volymer eller bara ett fåtal typer av beräkningar som skall utföras är en mjuk kärna mest fördelaktig, främst av ekonomiska skäl. Likaså om krav finns på att processorarkitekturen är anpassad efter specifika önskemål. / The purpose of the master thesis has been implementation of a performance comparison between hard and soft CPU cores integrated in FPGA, in this case, a Virtex4 FX12 from Xilinx. Test designs for the various kernels have been developed, where the amount of clock cycles to carry out a set of calculations have been measured. In particular, the algorithm Fast Fourier Transform and its inverse have been studied. The cores that have been tested are the soft MicroBlaze developed by Xilinx, and the hard PowerPC 405. The results state that the performance of the soft kernel was 65% of the hard one. In addition to performance tests, a further theoretical comparison of the two kernels has been made. On the basis of the above it has been concluded that when small quantities of FPGA-circuits are needed or several different calculations have to be done, a hard core is preferable. If there are larger volumes needed or just a few types of calculations to be made, a soft core is advantageous, primarily for economic reasons, as is the case if there is requirement of a processor core tailored for specific needs.

<p> </p><p>Examensarbetsuppgiften har gått ut på att genomföra en prestandajämförelse mellan en hård och en mjuk processorkärna integrerad i en FPGA, i detta fall, en Virtex4 FX12 från Xilinx.</p><p>System med de olika kärnorna har tagits fram, där antalet klockcykler för att genomföra olika beräkningar har mäts. Bland annat har algoritmen Fast Fourier Transform och dess invers beräknats för en vektor.</p><p>De kärnor som har provats är den mjuka MicroBlaze framtagen av Xilinx samt den hårda PowerPC 405. Prestandan för systemet med mjuk kärna var 65 % av det med hård kärna</p><p>Förutom prestandamätningarna har en vidare teoretisk jämförelse mellan kärnorna genomförts. Utifrån den har slutsatsen dragits att när man behöver små volymer av FPGA-kretsar eller flera olika beräkningar skall göras är FPGAer med hård kärna att föredra. Om det är större volymer eller bara ett fåtal typer av beräkningar som skall utföras är en mjuk kärna mest fördelaktig, främst av ekonomiska skäl. Likaså om krav finns på att processorarkitekturen är anpassad efter specifika önskemål.</p> / <p>The purpose of the master thesis has been implementation of a performance comparison between hard and soft CPU cores integrated in FPGA, in this case, a <em>Virtex4 FX12</em> from Xilinx.</p><p>Test designs for the various kernels have been developed, where the amount of clock cycles to carry out a set of calculations have been measured. In particular, the algorithm Fast Fourier Transform and its inverse have been studied.</p><p>The cores that have been tested are the soft MicroBlaze developed by Xilinx, and the hard PowerPC 405. The results state that the performance of the soft kernel was 65% of the hard one.</p><p>In addition to performance tests, a further theoretical comparison of the two kernels has been made. On the basis of the above it has been concluded that when small quantities of FPGA-circuits are needed or several different calculations have to be done, a hard core is preferable. If there are larger volumes needed or just a few types of calculations to be made, a soft core is advantageous, primarily for economic reasons, as is the case if there is requirement of a processor core tailored for specific needs.</p>

Orientador: Guido Costa Souza de Araujo / Dissertação (mestrado) - Universidade Estadual de Campinas, Instituto de Computação / Made available in DSpace on 2018-08-11T00:36:00Z (GMT). No. of bitstreams: 1 Souza_MaxwellMonteiroAndradede_M.pdf: 1735414 bytes, checksum: 76715c4172c656603702b765b56a679f (MD5) Previous issue date: 2008 / Resumo: Tradução binária dinâmica consiste em permitir que programas originalmente compilados para uma determinada arquitetura, executem sobre um nova arquitetura sem a necessidade de recompilação. Esta técnica pode ser usada como ferramenta de migração de aplicações entre arquiteturas ou até mesmo para permitir que uma aplicação execute sobre várias arquiteturas de forma transparente. A tradução binária dinâmica também permite que otimizações, não possíveis em tempo de compilação, sejam feitas em tempo de execução. ISAMAP é um sistema de tradução binária orientado a especificações de mapeamento de instruções entre um Conjunto de Instruções (ISA) origem e um ISA alvo. Em ISAMAP seqüências de instruções da ISA alvo são associadas á instruções da ISA origem, permitindo um mapeamento rápido e otimizado. Atualmente o ISAMAP realiza tradução binária de código PowerPC 32 para código x86 / Abstract: The main role of Dynamic Binary Translation is the capability of running applications compiled for a specific architecture over a totally diferent one without sources recompiling. This technique can be used neither in legacy code migration or in a transparent run-time environment to run applications of different arquitectures. Dynamic Binary Translation also offers otimizations possibilities once informations about application run-time behaviour are available. The ISAMAP is a mapping instructions driven dynamic binary translation system that makes able a mapping between two differents arquitectures. Instructions sequence of the source ISA are mapped to target ISA instructions, providing a fast and optimized mapping. In the current state ISAMAP translates PowerPC 32 binary code to x86 binary / Mestrado / Geração Dinamica de Codigo / Mestre em Ciência da Computação

With the advance of facial recognition technology, many related applications such as the clearance of specific facilities, air port security, video camera surveillance, and personnel recognition. To maximize working efficiency and reduce human resource, the platform used for facial recognition should possess both low cost, multimedia performance, and the ease of use. Among the list of available platforms, a IBM CELL multi-core based platform that features the aforementioned advantages is used to manifest our work. To meet the demand of recognition accuracy, a recognition algorithms using features low error rate and regular data patterns are adopted. These algorithms are carried out in two parts: Modified Census Transform (MCT) and hypotheses of human facial calculation. The multi-point average value required by the MCT is obtained through parallel processing, and potential improvement in recognition efficiency is possible if wider data paths are used. A PlayStation 3 (PS3) platform equipped with the IBM CELL multi-core processor is used in this thesis. The IBM CELL multi-core processor consists of a PowerPC Processor Element (PPE) and 8 Synergistic Processor (SPE), which forms a heterogeneous multi-core system. This system is capable of parallelizing thread-level and data-level data words, which can meet the demand of high data bandwidth and data parallelization. By using this platform to accelerate the processing of facial recognition, simulation results suggest that the execution efficiency is improved by 24 times when compared with a single core SPE. The simulation also reveals that the use of parallelization of processing facial recognition data feasible. In the future, improved algorithms can be applied to improve the accuracy of facial recognition.

<p>Embedded microcomputers are used in a wide range of applications nowadays. Avionics is one of these areas and requires extra attention regarding reliability and determinism. Thus, these issues should also be born in mind in addition to performance when evaluating embedded microcomputers.</p><p>This master thesis suggests a framework for performance evaluation of two members of the PowerPC microprocessor family, namely the MPC5554 from Freescale and PPC440EPx from AMCC, and analyzes the results within and between these processors. The framework can be generalized to be used in any microprocessor family, if required.</p><p>Apart from performance evaluation, this thesis also suggests also a new terminology by introducing the concept of determinism levels to be able to estimate determinism issues in avionics applications more clearly, which is crucial regarding the requirements and working conditions of this very application. Such estimation does not include any practical results as in performance evaluation, but rather remains theoretical. Similar to Automark™ used by AutoBench™ in the EEMBC Benchmark Suite, we introduce a new performance metric score that we call ”Aviomark” and we carry out a detailed comparison of Aviomark with the traditional Automark™ score to be able to see how Aviomark differs from Automark™ in behavior.</p><p>Finally, we have developed a graphical user interface (GUI) which works in parallel with the Green Hills MULTI Integrated Development Environment (IDE) in order to simplify and automate the evaluation process. By the help of the GUI, the users will be able to easily evaluate their specific PowerPC processors by starting the debugging from MULTI IDE.</p>

The emergence of a multitude of bandwidth hungry multimedia applications has ex- acerbated the need for multi-gigabit wireless solutions and made it out of the reach of conventional WLAN technology (802.11a, b and g). This thesis presents a system on chip which demonstrates the potential of 60GHz transceivers. This system is based on an FPGA board on which a GNU/Linux kernel has been run. This document will give some insight on the design process as well as on the finished product. Both the hardware and the software parts of the design are presented. This document is organized as follow. Chapter I presents an overview of the problem to be solved and some insight on the motivation to work at 60GHz. Chapter II gives a high level view of the multimedia processor that has been designed and implemented. Chapters III and IV respectively give more detail on the hardware parts and on the software components of the pro ject. Finally, Chapter V draws the conclusion of this work and presents the future of the work that has been started to enhance this multimedia processor.

Realtidssystem ställer hårda krav på dess ingående mjukvaras temporala beteende. Programmen måste bete sig deterministiskt och ge svar inom satta tidsgränser. Med hårda krav följer större behov av verktyg att testa koden med. WCET (Worst Case Execution Time)-analys har som mål att finna en övre gräns för ett programs exekveringstid. SWEET (SWEdish Execution Time) är ett verktyg för WCET-analys utvecklat av en forskargrupp vid Mälardalens Högskola. PowerPC är en klassisk processorarkitektur som utvecklades av Apple, Motorola och IBM och släpptes 1991. Den har bland annat använts av Apple i äldre versioner av deras Macintosh-datorer och i TV-spelskonsoler såsom Nintendo GameCube och är stor inom inbyggda system. Tidigare har endast analys av källkod, C, varit möjlig i SWEET. Målet för detta examensarbete var att möjliggöra analys av körbara program för vilka källkoden ej är tillgänglig, Detta gjordes genom att konstruera en översättare från PowerPC-binärer till det programformat som SWEET använder för sina statiska analyser, ALF, med hjälp av tredjepartsverktyget aiT från AbsInt GmbH. Resultatet blev en med undantag för flyttalsinstruktioner komplett översättare av PowerPC-program till ALF-kod. De flesta genererade programfiler som har testats i SWEET har gett lyckat resultat. / Real-time systems put tough timing requirements on the software running on them. The programs must behave deterministically and respond within set time limits. With these demands comes a higher demand on verification tools. The goal of a WCET (Worst Case Execution Time) analysis is to derive the upper bound of a program's execution time. SWEET (SWEdish Execution Time) is a tool for WCET analysis developed by a research group at Mälardalen University. PowerPC is a classic processor architecture that was developed by Apple, Motorola and IBM and was released in 1991. It has been used in older versions of Apple's Macintosh computers and in video game consoles such as the GameCube from Nintendo, and is a popular choice for embedded solutions. Previously you could only do analyses on code generated from C in SWEET. The goal of this MSC thesis was to construct a converter from PowerPC binaries to the program format that SWEET uses for its analyses, ALF, with the help of the third-party tool aiT from AbsInt GmbH. The result is a - with the exception of floating-point instructions - complete converter from PowerPC programs to ALF. Most of the generated program files have been tested within SWEET with successful results.

Embedded microcomputers are used in a wide range of applications nowadays. Avionics is one of these areas and requires extra attention regarding reliability and determinism. Thus, these issues should also be born in mind in addition to performance when evaluating embedded microcomputers. This master thesis suggests a framework for performance evaluation of two members of the PowerPC microprocessor family, namely the MPC5554 from Freescale and PPC440EPx from AMCC, and analyzes the results within and between these processors. The framework can be generalized to be used in any microprocessor family, if required. Apart from performance evaluation, this thesis also suggests also a new terminology by introducing the concept of determinism levels to be able to estimate determinism issues in avionics applications more clearly, which is crucial regarding the requirements and working conditions of this very application. Such estimation does not include any practical results as in performance evaluation, but rather remains theoretical. Similar to Automark™ used by AutoBench™ in the EEMBC Benchmark Suite, we introduce a new performance metric score that we call ”Aviomark” and we carry out a detailed comparison of Aviomark with the traditional Automark™ score to be able to see how Aviomark differs from Automark™ in behavior. Finally, we have developed a graphical user interface (GUI) which works in parallel with the Green Hills MULTI Integrated Development Environment (IDE) in order to simplify and automate the evaluation process. By the help of the GUI, the users will be able to easily evaluate their specific PowerPC processors by starting the debugging from MULTI IDE.

La contribution de cette thèse concerne le développement et la conception d’un système multimédia embarqué basé sur l’approche de conception conjointe matérielle/logicielle (codesign). Il en résulte ainsi la constitution d’une bibliothèque de modules IP (Intellectual Property) pour les applications vidéo. Dans ce contexte, une plateforme matérielle de validation a été réalisée servant au préalable à l’évaluation de l’approche de conception en codesign pour l’étude d’algorithmes de traitement vidéo. Nous nous sommes ainsi intéressés en particulier à l’étude et à l’implantation de la norme de décompression vidéo H.264/AVC. Pour la validation fonctionnelle, l’ensemble du développement a été réalisé autour d’une carte Xilinx à base d’un circuit programmable FPGA Xilinx Virtex-5en mettant en œuvre le processeur hardcore PowerPC du circuit programmable dans l’environnement logiciel Linux pour l’embarqué. Le décodeur H.264/AVC ainsi développé comporte différents accélérateurs matériels pour la transformation inverse ainsi que le filtre anti-blocs. Nous avons pu tester les performances au regard du respect des contraintes temporelles en intégrant une extension temps réel à la plateforme de validation suivant différentes conditions de stress du système. L’extension temps réel Xenomai fournit ainsi une réponse adéquate aux problématiques de charge du système et de maîtrise des contraintes temporelles inhérentes à tout système de traitement vidéo tout en autorisant aussi l’utilisation d’applications classiques mises en œuvre dans l’environnement standard Linux embarqué. / The main contribution of this thesis concerns the development and the design of an embedded system for multimedia based on the codesign approach (HW/SW). Towards this end, a library off lexible IP cores (Intellectual Property) for video applications was created. In this context, a hardware platform was used for evaluation of the codesign-based approach in order to study video processingalgorithms. Thus, we particularly focused on the study and the implementation of H.264/AVC decoder. For functional validation, the entire development was carried out around a FPGA Virtex-5 Xilinx board embedding a hardcore PowerPC processor running embedded Linux operating system. The H.264/AVC developed decoder consists of hardware accelerators for the inverse transformation and the deblocking filter. We evaluated the performances in terms of respect of temporal constraints by integrating a real-time extension to the validation platform under different stress conditions. The Xenomai real-time extension has proven its high performance level of compliance with hard real-time constraints. This extension offers a real solution for real-time behavior without limiting the use of conventional applications implemented traditionally in a time sharing environment.