With the advance of facial recognition technology, many related applications such as the clearance of specific facilities, air port security, video camera surveillance, and personnel recognition. To maximize working efficiency and reduce human resource, the platform used for facial recognition should possess both low cost, multimedia performance, and the ease of use. Among the list of available platforms, a IBM CELL multi-core based platform that features the aforementioned advantages is used to manifest our work. To meet the demand of recognition accuracy, a recognition algorithms using features low error rate and regular data patterns are adopted. These algorithms are carried out in two parts: Modified Census Transform (MCT) and hypotheses of human facial calculation. The multi-point average value required by the MCT is obtained through parallel processing, and potential improvement in recognition efficiency is possible if wider data paths are used. A PlayStation 3 (PS3) platform equipped with the IBM CELL multi-core processor is used in this thesis. The IBM CELL multi-core processor consists of a PowerPC Processor Element (PPE) and 8 Synergistic Processor (SPE), which forms a heterogeneous multi-core system. This system is capable of parallelizing thread-level and data-level data words, which can meet the demand of high data bandwidth and data parallelization. By using this platform to accelerate the processing of facial recognition, simulation results suggest that the execution efficiency is improved by 24 times when compared with a single core SPE. The simulation also reveals that the use of parallelization of processing facial recognition data feasible. In the future, improved algorithms can be applied to improve the accuracy of facial recognition.

La contribution de cette thèse concerne le développement et la conception d’un système multimédia embarqué basé sur l’approche de conception conjointe matérielle/logicielle (codesign). Il en résulte ainsi la constitution d’une bibliothèque de modules IP (Intellectual Property) pour les applications vidéo. Dans ce contexte, une plateforme matérielle de validation a été réalisée servant au préalable à l’évaluation de l’approche de conception en codesign pour l’étude d’algorithmes de traitement vidéo. Nous nous sommes ainsi intéressés en particulier à l’étude et à l’implantation de la norme de décompression vidéo H.264/AVC. Pour la validation fonctionnelle, l’ensemble du développement a été réalisé autour d’une carte Xilinx à base d’un circuit programmable FPGA Xilinx Virtex-5en mettant en œuvre le processeur hardcore PowerPC du circuit programmable dans l’environnement logiciel Linux pour l’embarqué. Le décodeur H.264/AVC ainsi développé comporte différents accélérateurs matériels pour la transformation inverse ainsi que le filtre anti-blocs. Nous avons pu tester les performances au regard du respect des contraintes temporelles en intégrant une extension temps réel à la plateforme de validation suivant différentes conditions de stress du système. L’extension temps réel Xenomai fournit ainsi une réponse adéquate aux problématiques de charge du système et de maîtrise des contraintes temporelles inhérentes à tout système de traitement vidéo tout en autorisant aussi l’utilisation d’applications classiques mises en œuvre dans l’environnement standard Linux embarqué. / The main contribution of this thesis concerns the development and the design of an embedded system for multimedia based on the codesign approach (HW/SW). Towards this end, a library off lexible IP cores (Intellectual Property) for video applications was created. In this context, a hardware platform was used for evaluation of the codesign-based approach in order to study video processingalgorithms. Thus, we particularly focused on the study and the implementation of H.264/AVC decoder. For functional validation, the entire development was carried out around a FPGA Virtex-5 Xilinx board embedding a hardcore PowerPC processor running embedded Linux operating system. The H.264/AVC developed decoder consists of hardware accelerators for the inverse transformation and the deblocking filter. We evaluated the performances in terms of respect of temporal constraints by integrating a real-time extension to the validation platform under different stress conditions. The Xenomai real-time extension has proven its high performance level of compliance with hard real-time constraints. This extension offers a real solution for real-time behavior without limiting the use of conventional applications implemented traditionally in a time sharing environment.