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Fast Hardware Algorithm for Division in GF(2m) Based on the Extended Euclid's Algorithm With Parallelization of Modular Reductions

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1. http://hdl.handle.net/2237/13911
2. http://dx.doi.org/10.1109/TCSII.2009.2024253
3. 1549-7747
4. Circuits and Systems II: Express Briefs, IEEE Transactions on Aug. 2009 v.56, n.8, p.644 - 648

Identifer	oai:union.ndltd.org:NAGOYA/oai:ir.nul.nagoya-u.ac.jp:2237/13911
Date	08 1900
Creators	Kobayashi, Katsuki, Takagi, Naofumi
Publisher	IEEE
Source Sets	Nagoya University
Language	English
Detected Language	English
Type	Article(publisher)
Rights	©20xx IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.