Real world is analog but the processing of signals can best be done in digital
domain. So the need for Analog to Digital Converters(ADCs) is ever rising as
more and more applications set in. With the advent of mobile technology, power
in electronic equipment is being driven down to get more battery life. Because of
their ubiquitous nature, ADCs are prime blocks in the signal chain in which power
is intended to be reduced. In this thesis, four techniques to reduce power in high
speed pipelined ADCs have been proposed. The first is a capacitor and opamp
sharing technique that reduces the load on the first stage opamp by three fold.
The second is a capacitor reset technique that aids removing the sample and hold
block to reduce power. The third is a modified MDAC which can take rail-to-rail
input swing to get an extra bit thus getting rid of a power hungry opamp. The
fourth is a hybrid architecture which makes use of an asynchronous SAR ADC
as the backend of a pipelined ADC to save power. Measurement and simulation
results that prove the efficiency of the proposed techniques are presented. / Graduation date: 2009
| Identifer | oai:union.ndltd.org:ORGSU/oai:ir.library.oregonstate.edu:1957/10294 |
| Date | 12 January 2009 |
| Creators | Lingam, Naga Sasidhar |
| Contributors | Moon, Un-Ku, Hanumolu, PavanKumar |
| Source Sets | Oregon State University |
| Language | en_US |
| Detected Language | English |
| Type | Thesis |
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