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Previous issue date: 2012-08-29 / Advances related to integrated circuit manufactring technologies push the complexity and the number of functionalities in electronic products. The literature points out that in 2015 behavioral design will demand 50% of the whole design effort, what indicates a major need for developing circuit design automation tools. Besides that, the design of current circuits employs the synchronous design paradigm prioritarily. However this design paradigma jointly with the increase of complexity imposes relevant restriction with regard to energy consumption and power dissipation design constraints. This works presents an alternative to some of the cited problems, proposing an environment for the generation and evaluation of intrachip networks. These networks allow interconnect processing modules operating at different operating frequencies, as well as help to guarantee the fulfillment of temporal restrictions temporais imposed by the traffic requirements of such modules. During the network generation step, the proposed environment allows selecting the network characteristiscs at design time, including individual router operating frequencies. Besides network generation, the environment also enables evaluating temporal contraints for several distinct traffic models, supporting the parameterized generation of traffic to exercise the network. This characteristic offer new alternatives to reduce the design effort of intrachip network for electronic systems still in the early phases of system specification. This occurs because the environment enables the visualization of the network behavior, demonstrating if this fulfills or not the expected requirements for some give traffic scenario. / Os avan?os relacionados ? tecnologia de fabrica??o de circuitos integrados impulsionam a complexidade e o n?mero de funcionalidades dos produtos eletr?nicos. A literatura aponta que at? 2015 tarefas do n?vel comportamental ocupar?o cerca de 50% do esfor?o de projeto, o que refor?a a necessidade do desenvolvimento de ferramentas de automa??o e gera??o autom?tica de circuitos. Al?m disso, o projeto de circuitos atuais faz uso prioritariamente do paradigma de projeto s?ncrono, que associado ao crescimento da complexidade dos mesmos imp?e restri??es importantes com rela??o ao consumo de energia e ? dissipa??o de pot?ncia. Este trabalho apresenta uma solu??o alternativa a alguns dos problemas citados, pela proposta de um ambiente de gera??o e avalia??o de redes intrachip. Tais redes permitem, al?m de conectar m?dulos de processamento que operem em diferentes frequ?ncias, ajudar a garantir o atendimento de restri??es temporais impostas pelos requisitos de tr?fego destes m?dulos. Durante a gera??o da rede, o ambiente permite em tempo de projetos selecionar caracter?sticas da mesma, tais como as frequ?ncias de opera??o dos roteadores, de forma individualizada. Al?m da gera??o da rede, o ambiente ainda habilita avaliar restri??es temporais de diferentes modelos de tr?fegos, dando suporte ? gera??o parametrizada de tr?fego para exercitar a rede. Esta caracter?stica oferece alternativas para reduzir o esfor?o do projeto dos sistemas eletr?nicos ainda nas fases de especifica??o de requisitos do sistema. Isto ocorre por que o ambiente facilita a visualiza??o do comportamento de um modelo de rede, demonstrando se o mesmo atende ou n?o a requisitos esperados para um cen?rio de tr?fego.
| Identifer | oai:union.ndltd.org:IBICT/oai:tede2.pucrs.br:tede/5277 |
| Date | 29 August 2012 |
| Creators | Schemmer, Raffael Bottoli |
| Contributors | Calazans, Ney Laert Vilar |
| Publisher | Pontif?cia Universidade Cat?lica do Rio Grande do Sul, Programa de P?s-Gradua??o em Ci?ncia da Computa??o, PUCRS, BR, Faculdade de Inform?ca |
| Source Sets | IBICT Brazilian ETDs |
| Language | Portuguese |
| Detected Language | English |
| Type | info:eu-repo/semantics/publishedVersion, info:eu-repo/semantics/masterThesis |
| Format | application/pdf |
| Source | reponame:Biblioteca Digital de Teses e Dissertações da PUC_RS, instname:Pontifícia Universidade Católica do Rio Grande do Sul, instacron:PUC_RS |
| Rights | info:eu-repo/semantics/openAccess |
| Relation | 1974996533081274470, 500, 600, 1946639708616176246 |
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