A 3.3V 8-bit 250MSample/sec synchronous comparison current-mode analog to digital converter is described in this thesis. The high bits and low bits are realized by two 4-bit synchronous comparison A/Ds. The 4-bit ADC has 4 reference output, which are compared with Iin, to carry out 4-bit synchronous digital output. The reference produce circuit architecture comprises a quantification current source circuit and a thermal-to-analog (DAC) circuit. In this IADC architecture, each 4-bit pipelined stage consists of current-mirror circuits, quantification current source, and current comparator elements. This architecture can achieve a very high conversion rate due to the lack of sample/hold circuit. From HSPICE simulation results, the proposed IADC can achieve 8-bit resolution with 250MHz sampling rate. It is designed by using TSMC 0.35£gm COMS 2P4M technology. It occupies an area of 420um ¡Ñ 550um and has power consumption of 13.24mW from a 3.3-V supply. That DNL is +/- 0.5LSB, and INL is +/- 0.65LSB are achieved.
Source : VLSI 2005 submitted.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0719105-153559 |
| Date | 19 July 2005 |
| Creators | Fan, Gang-Jin |
| Contributors | none, none, none, none, Jyi-Tsong Lin |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0719105-153559 |
| Rights | unrestricted, Copyright information available at source archive |
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