Indiana University-Purdue University Indianapolis (IUPUI) / Recent ULSI (ultra large scale integration) technology emphasizes small size devices, featuring low power and high switching speed. Moore's law has been followed successfully in scaling down the silicon device in order to enhance the level of integration with high performances until conventional devices failed to cop up with
further scaling due to limitations with ballistic effects, and challenges with accommodating dopant fluctuation, mobility degradation, among other device parameters. Recently, Graphene based devices o ered alternative approach, featuring small size and high performances. This includes high carrier mobility, high carrier density, high robustness, and high thermal conductivity. These unique characteristics made the Graphene devices attractive for high speed electronic architectures. In this research, Graphene devices were integrated into applications with analog, digital, and mixed signals based systems.
Graphene devices were briefly explored in electronics applications since its first
model developed by the University of Illinois, Champaign in 2013. This study emphasizes the validation of the model in various applications with analog, digital, and
mixed signals. At the analog level, the model was used for voltage and power amplifiers; classes A, B, and AB. At the digital level, the device model was validated within the universal gates, adders, multipliers, subtractors, multiplexers, demultiplexers, encoders, and comparators. The study was also extended to include Graphene devices
for serializers, the digital systems incorporated into the data structure storage. At
the mixed signal level, the device model was validated for the DACs/ADCs. In all components, the features of the new devices were emphasized as compared with the existing silicon technology. The system functionality and dynamic performances were
also elaborated. The study also covered the linearity characteristics of the devices
within full input range operation.
GNRFETs with a minimum channel length of 10nm and an input voltage 0.7V
were considered in the study. An electronic design platform ADS (Advanced Design
Systems) was used in the simulations. The power amplifiers showed noise figure as
low as 0.064dbs for class A, and 0.32 dbs for class B, and 0.69 dbs for class AB power
amplifiers. The design was stable and as high as 5.12 for class A, 1.02 for class B,
and 1.014 for class AB. The stability factor was estimated at 2GHz operation. The
harmonics were as low as -100 dbs for class A, -60 dbs for class B, and -50dbs for class AB, all simulated at 1GHz. The device was incorporated into ADC system, and as
low as 24.5 micro Watt power consumption and 40 nsec rise time were observed. Likewise, the DAC showed low power consumption as of 4.51 micro Watt. The serializer showed as minimum power consumption of the order of 0.4mW.
These results showed that these nanoscale devices have potential future for high-speed communication systems, medical devices, computer architecture and dynamic Nano electromechanical (NEMS) which provides ultra-level of integration, incorporating embedded and IoT devices supporting this technology. Results of analog and digital components showed superiority over other silicon transistor technologies in their ultra-low power consumption and high switching speed.
| Identifer | oai:union.ndltd.org:IUPUI/oai:scholarworks.iupui.edu:1805/18945 |
| Date | 05 1900 |
| Creators | Patnala, Mounica |
| Contributors | Rizkalla, Maher E., King, Brian S., Sharkawy, Mohamed El, Ytterdal, Trond |
| Source Sets | Indiana University-Purdue University Indianapolis |
| Language | English |
| Detected Language | English |
| Type | Thesis |
| Rights | Attribution-NonCommercial-NoDerivs 3.0 United States, http://creativecommons.org/licenses/by-nc-nd/3.0/us/ |
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