Indiana University-Purdue University Indianapolis (IUPUI) / Recent ULSI (ultra large scale integration) technology emphasizes small size devices, featuring low power and high switching speed. Moore's law has been followed successfully in scaling down the silicon device in order to enhance the level of integration with high performances until conventional devices failed to cop up with further scaling due to limitations with ballistic effects, and challenges with accommodating dopant fluctuation, mobility degradation, among other device parameters. Recently, Graphene based devices o ered alternative approach, featuring small size and high performances. This includes high carrier mobility, high carrier density, high robustness, and high thermal conductivity. These unique characteristics made the Graphene devices attractive for high speed electronic architectures. In this research, Graphene devices were integrated into applications with analog, digital, and mixed signals based systems. Graphene devices were briefly explored in electronics applications since its first model developed by the University of Illinois, Champaign in 2013. This study emphasizes the validation of the model in various applications with analog, digital, and mixed signals. At the analog level, the model was used for voltage and power amplifiers; classes A, B, and AB. At the digital level, the device model was validated within the universal gates, adders, multipliers, subtractors, multiplexers, demultiplexers, encoders, and comparators. The study was also extended to include Graphene devices for serializers, the digital systems incorporated into the data structure storage. At the mixed signal level, the device model was validated for the DACs/ADCs. In all components, the features of the new devices were emphasized as compared with the existing silicon technology. The system functionality and dynamic performances were also elaborated. The study also covered the linearity characteristics of the devices within full input range operation. GNRFETs with a minimum channel length of 10nm and an input voltage 0.7V were considered in the study. An electronic design platform ADS (Advanced Design Systems) was used in the simulations. The power amplifiers showed noise figure as low as 0.064dbs for class A, and 0.32 dbs for class B, and 0.69 dbs for class AB power amplifiers. The design was stable and as high as 5.12 for class A, 1.02 for class B, and 1.014 for class AB. The stability factor was estimated at 2GHz operation. The harmonics were as low as -100 dbs for class A, -60 dbs for class B, and -50dbs for class AB, all simulated at 1GHz. The device was incorporated into ADC system, and as low as 24.5 micro Watt power consumption and 40 nsec rise time were observed. Likewise, the DAC showed low power consumption as of 4.51 micro Watt. The serializer showed as minimum power consumption of the order of 0.4mW. These results showed that these nanoscale devices have potential future for high-speed communication systems, medical devices, computer architecture and dynamic Nano electromechanical (NEMS) which provides ultra-level of integration, incorporating embedded and IoT devices supporting this technology. Results of analog and digital components showed superiority over other silicon transistor technologies in their ultra-low power consumption and high switching speed.

Recent ULSI (ultra large scale integration) technology emphasizes small size devices, featuring low power and high switching speed. Moore's law has been followed<br>successfully in scaling down the silicon device in order to enhance the level of integration with high performances until conventional devices failed to cop up with further scaling due to limitations with ballistic effects, and challenges with accommodating dopant fluctuation, mobility degradation, among other device parameters. Recently, Graphene based devices offered alternative approach, featuring small size<br>and high performances. This includes high carrier mobility, high carrier density, high robustness, and high thermal conductivity. These unique characteristics made the<br>Graphene devices attractive for high speed electronic architectures. In this research, Graphene devices were integrated into applications with analog, digital, and mixed<br>signals based systems.<br>Graphene devices were briefly explored in electronics applications since its first model developed by the University of Illinois, Champaign in 2013. This study emphasizes the validation of the model in various applications with analog, digital, and mixed signals. At the analog level, the model was used for voltage and power amplifiers; classes A, B, and AB. At the digital level, the device model was validated within the universal gates, adders, multipliers, subtractors, multiplexers, demultiplexers, encoders, and comparators. The study was also extended to include Graphene devices<br><div>for serializers, the digital systems incorporated into the data structure storage. At the mixed signal level, the device model was validated for the DACs/ADCs. In all components, the features of the new devices were emphasized as compared with the existing silicon technology. The system functionality and dynamic performances were also elaborated. The study also covered the linearity characteristics of the devices within full input range operation.</div><div>GNRFETs with a minimum channel length of 10nm and an input voltage 0.7V were considered in the study. An electronic design platform ADS (Advanced Design<br>Systems) was used in the simulations. The power amplifiers showed noise figure as low as 0.064dbs for class A, and 0.32 dbs for class B, and 0.69 dbs for class AB power<br>amplifiers. The design was stable and as high as 5.12 for class A, 1.02 for class B, and 1.014 for class AB. The stability factor was estimated at 2GHz operation. The harmonics were as low as -100 dbs for class A, -60 dbs for class B, and -50dbs for class AB, all simulated at 1GHz. The device was incorporated into ADC system, and as<br>low as 24.5 micro Watt power consumption and 40 nsec rise time were observed. Likewise, the DAC showed low power consumption as of 4.51 micro Watt. The serializer showed as minimum power consumption of the order of 0.4mW. <br></div><div>These results showed that these nanoscale devices have potential future for high-speed communication systems, medical devices, computer architecture and dynamic<br>Nano electromechanical (NEMS) which provides ultra-level of integration, incorporating embedded and IoT devices supporting this technology. Results of analog and<br>digital components showed superiority over other silicon transistor technologies in their ultra-low power consumption and high switching speed.<br></div><div><br></div>

Approved for public release, distribution is unlimited / This research involves the development of a human-body motion tracking system constructed with the use of commercial off-the-shelf (COTS) components. The main component of the system investigated in this thesis is the Control Interface Unit (CIU). The CIU is a component designed to receive data from the magnetic, angular rate, and gravity (MARG) sensors and prepare them to be transmitted through a wireless configuration. A simple and effective algorithm is used to filter the sensor data without singularities, providing the measured attitude in the quaternion form for each human limb. Initial calibration of the MARG sensors is also performed with the use of linear calibrating algorithms. The testing and evaluation of the whole system is performed by MATLABʼ and SIMULINKʼ simulations, and by the realtime visualization using a human avatar designed with the X3D graphics specifications. Through this research, it is discovered that the MARG sensors had to be redesigned to overcome an erratum on the Honeywell magnetometer HMC1051Z data sheet. With the redesigned MARG sensors, the testing results showed that the CIU was performing extremely well. The overall motion tracking system is capable of tracking human body limb motions in real time. / Lieutenant Junior Grade, Hellenic Navy

Dynamic Voltage Scaling (DVS) and Adaptive body bias (ABB) techniques respectively try to reduce the dynamic and static power components of an integrated circuit. Ideally, the two techniques can be combined to find the optimal operating voltages (VDD and VBB) to minimize power consumption. A combination of the DVS and ABB may warrant the circuit to operate at voltages (supply and body bias) different from the values specified by the two methods working independently. Also, this VDD and VBB values for minimal power consumption varies with the workload of the circuit. The workload can be used as an index to select the optimal VDD/VBB values to minimize the total power consumption. This paper examines the optimal voltages for minimal power operation for typical data path circuits like adders and multiply-accumulate (MAC) units across various process, voltage, and temperature conditions and under different workloads. In addition, a workload based look up table to minimize the power consumption is also proposed. Simulation results for an adder and a multiply-accumulate circuit block indicate a power saving of 12-30% over standard DVS scheme.