PCM test structures are commonly used to check the produced wafers from the standpoint of the technologist. In general
these structures are managed inside the FAB and are focused on standard device properties. Hence their development and
analysis is not driven by analog circuit blocks, which are sensitive or often used. Especially for DFM/Y of analog circuits
the correlation between design and technology has to be defined. The knowledge of electrical behavior of test structures
helps to improve the designer's sensitivity to technological questions.
This paper presents a method to bring the PCM methodology into the analog circuit design to improve design performance,
yield estimation and technology correlation. We show how both analog circuit and PCM blocks can be simulated and
analyzed in the design phase.
| Identifer | oai:union.ndltd.org:DRESDEN/oai:qucosa.de:swb:ch1-200700919 |
| Date | 08 June 2007 |
| Creators | Sobe, Udo, Rooch, Karl-Heinz, Mörtl, Dietmar |
| Contributors | TU Chemnitz, Fakultät für Informatik |
| Publisher | Universitätsbibliothek Chemnitz |
| Source Sets | Hochschulschriftenserver (HSSS) der SLUB Dresden |
| Language | English |
| Detected Language | English |
| Type | doc-type:conferenceObject |
| Format | application/pdf, text/plain, application/zip |
| Relation | dcterms:isPartOfhttp://nbn-resolving.de/urn:nbn:de:swb:ch1-200700815 |
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