Neutral gas pressure measurements in low Earth orbit (LEO) can facilitate the monitoring of atmospheric gravity waves, which can trigger instabilities that severely disrupt radio frequency communication signals. The Space Neutral Pressure Instrument (SNeuPI) is a low-power instrument detecting neutral gas density in order to determine neutral gas pressure. SNeuPI consists of an ionization chamber and a logarithmic electrometer circuit. The Rev. 1 SNeuPI electrometer prototype does not function as designed. A Rev. 2 electrometer circuit must be designed and its performance characterized across specified operating temperature and input current ranges. This document presents a design topology for the Rev. 2 electrometer and a derivation of the theoretical circuit transfer function. Component selection and layout are discussed. A range of predicted operating input currents is calculated using modeled neutral density data for a range of local times, altitudes, and latitudes corresponding to the conditions expected for the Lower Atmosphere/Ionosphere Coupling Experiment (LAICE) CubeSat mission. Laboratory test setups for measurements performed both under vacuum and at atmospheric pressure are documented in detail. Test procedures are presented to characterize the performance of the Rev. 2 electrometer at a range of controlled operating temperatures. The results of these tests are then extrapolated in order to predict the operation of the circuit at specified temperatures outside of the range controllable under laboratory test conditions. The logarithmic conformance, accuracy, sensitivity, power consumption, and deviations from expected response of the circuit are characterized. The results validate the electrometer for use under its expected flight conditions. / Master of Science

The profound digitization of modern microelectronic modules made Analog-to- Digital converters (ADC) key components in many systems. With resolutions up to 14bits and sampling rates in the 100s of MHz, the pipeline ADC is a prime candidate for a wide range of applications such as instrumentation, communications and consumer electronics. However, while past work focused on enhancing the performance of the pipeline ADC from an architectural standpoint, little has been done to individually address its fundamental building blocks. This work aims to achieve the latter by proposing design techniques to improve the performance of these blocks with minimal power consumption in low voltage environments, such that collectively high performance is achieved in the pipeline ADC. Towards this goal, a Recycling Folded Cascode (RFC) amplifier is proposed as an enhancement to the general performance of the conventional folded cascode. Tested in Taiwan Semiconductor Manufacturing Company (TSMC) 0.18?m Complementary Metal Oxide Semiconductor (CMOS) technology, the RFC provides twice the bandwidth, 8-10dB additional gain, more than twice the slew rate and improved noise performance over the conventional folded cascode-all at no additional power or silicon area. The direct auto-zeroing offset cancellation scheme is optimized for low voltage environments using a dual level common mode feedback (CMFB) circuit, and amplifier differential offsets up to 50mV are effectively cancelled. Together with the RFC, the dual level CMFB was used to implement a sample and hold amplifier driving a singleended load of 1.4pF and using only 2.6mA; at 200MS/s better than 9bit linearity is achieved. Finally a power conscious technique is proposed to reduce the kickback noise of dynamic comparators without resorting to the use of pre-amplifiers. When all techniques are collectively used to implement a 1Vpp 10bit 160MS/s pipeline ADC in Semiconductor Manufacturing International Corporation (SMIC) 0.18[mu]m CMOS, 9.2 effective number of bits (ENOB) is achieved with a near Nyquist-rate full scale signal. The ADC uses an area of 1.1mm2 and consumes 42mW in its analog core. Compared to recent state-of-the-art implementations in the 100-200MS/s range, the presented pipeline ADC uses the least power per conversion rated at 0.45pJ/conversion-step.

Time-interleaved analog-to-digital converters make use of parallelization to increase the rate at which an analog signal can be digitized. Using M channels at their maximum sampling frequency allows for an overall sampling frequency of M times the individual converters' sampling rate. However, the performance of interleaved systems suffers from mismatches between the sub-converters. Offset mismatches, gain mismatches, and timing mismatches all contribute to the degradation of the resolution of the ADC system. Offset and gain mismatches can be corrected for in the digital domain with minimal extra processing. However, the effects of timing mismatches (specifically, the magnitude of the spurious tones that are introduced) are dependent on the frequency of the input, so digital correction is not a trivial task. This makes a circuit-based correction mechanism a much more desirable solution to the problem. This work explores the effect of timing mismatches on interleaved analog-to-digital converter performance. A set of requirements is derived to specify the performance of a variable-delay circuit for the tuning of sample clocks. Since the mismatches can be composed of both fixed and random components, several candidate architectures are modeled for their delay and jitter performance. One candidate is selected for design, based on its jitter performance and on practical considerations. A practical implementation of the clock-adjustment circuit is designed, featuring low-noise differential clock paths with high precision delay adjustment. A means of testing the circuit and verifying the precision of adjustment is presented. The design is implemented for fabrication, and post-layout simulations are shown to demonstrate the feasibility and functionality of the design.

A simple methodology for determining the input referred offset voltage of comparators is presented. This in general is difficult as the output of a comparator is discrete valued. The method relies on a Monte-Carlo-Simulation with certain comparator input values and some postprocessing of the comparator output data. The comparator is always operated in its intended environment, there is no modification of the comparator itself nor some unusual stimuli required. There is also no known restriction for the type of comparators to be analyzed.

Time-interleaved analog-to-digital converters make use of parallelization to increase the rate at which an analog signal can be digitized. Using M channels at their maximum sampling frequency allows for an overall sampling frequency of M times the individual converters' sampling rate. However, the performance of interleaved systems suffers from mismatches between the sub-converters. Offset mismatches, gain mismatches, and timing mismatches all contribute to the degradation of the resolution of the ADC system. Offset and gain mismatches can be corrected for in the digital domain with minimal extra processing. However, the effects of timing mismatches (specifically, the magnitude of the spurious tones that are introduced) are dependent on the frequency of the input, so digital correction is not a trivial task. This makes a circuit-based correction mechanism a much more desirable solution to the problem. This work explores the effect of timing mismatches on interleaved analog-to-digital converter performance. A set of requirements is derived to specify the performance of a variable-delay circuit for the tuning of sample clocks. Since the mismatches can be composed of both fixed and random components, several candidate architectures are modeled for their delay and jitter performance. One candidate is selected for design, based on its jitter performance and on practical considerations. A practical implementation of the clock-adjustment circuit is designed, featuring low-noise differential clock paths with high precision delay adjustment. A means of testing the circuit and verifying the precision of adjustment is presented. The design is implemented for fabrication, and post-layout simulations are shown to demonstrate the feasibility and functionality of the design.

Diferente do projeto de sistemas digitais, no qual as técnicas de projeto e ferramentas CAD vêm apresentando uma crescente evolução acompanhada da redução de seus preços, o projeto de sistemas analógicos CMOS ainda apresenta uma forte correlação com a experiência do projetista. Dentro deste contexto, importantes fatores como caracterização de tecnologia, modelamento de dispositivos e metodologia de projeto devem ser considerados. Este trabalho apresenta um estudo destes importantes fatores necessários para se realizar o projeto de um sistema analógico com menor custo, bom desempenho e reduzido tempo de projeto. Primeiramente, é necessária uma extensa caracterização da tecnologia CMOS a ser usada, onde os parâmetros que descrevem as caracteristicas elétricas dos dispositivos são obtidos. A partir desta caracterização e das especificações requeridas para o circuito, é feita uma modelagem e sintese a fim de se obter as dimensões dos transistores. Ferramentas para a análise do desempenho elétrico são utilizadas a seguir, antes de se realizar a descrição geométrica (layout) do circuito. Com o layout pronto, uma nova simulação elétrica é feita incluindo os efeitos geométricos, incluindo-se os parasitas R, C e L extraídos do layout. Se os resultados forem satisfatórios, o circuito está pronto para fabricação; havendo degradação do desempenho esperado, uma nova iteração de projeto é realizada. Mais especificamente, este trabalho ilustra o processo de análise de vários circuitos analógicos, assim como as caracteristicas de cada circuito em questão, empregando diferentes metodologias de projeto. Uma metodologia de projeto convencional, baseada em modelos onde se obtém uma equação explícita para a corrente válida na região de operação de saturação do transistor, e uma metodologia de projeto baseada na caracteristica g,/ID do transistor, que apresenta uma sintese unificada, considerando todas as regiões de operação do transistor MOS. Os circuitos a serem analisados e projetados neste trabalho são blocos considerados básicos para construção da maioria dos sistemas analógicos usados atualmente, como, por exemplo, Moduladores Sigma-Delta. Tais blocos são amplificadores, comparadores e filtros analógicos. A metodologia de projeto, baseada em parâmetros do modelo elétrico, é apresentada, enfatizando a caracteristica ~,/ID do transistor. Simulações elétricas serão realizadas (esquemático e layout extraído) para cada bloco, validando-se o projeto para as especificações requeridas. / Design techniques and CAD tools for digital systems are advancing rapidly at decreasing cost, while CMOS analog circuit design is related mostly with the individual experience and background of the designer. Therefore, the design of an analog circuit depends on several factors such as a reliable design methodology, good modeling and circuit fabrication technology characterization. This work presents a study of these factors that allow an analog system to be designed with high quality and performance at low cost, in a reasonable design time. First, an extensive characterization of the technology must be developed, where a11 the parameters that describe the electrical properties of the device are obtained. When this task is complete, an extensive analysis and modeling is made, transforming specifications into circuits with the transistor dimensions calculated. This leads to another important task - using electrical simulation to predict the performance of the circuit. Once the performance goals are satisfied, the designer is faced with the task of geometrical description (layout) of the circuit. Once the layout is finished, it is necessary to include the geometrical effects in a post-extraction simulation. If the results are satisfactory, the circuit is ready for fabrication. In case the specifications are not met, new design iteration must be undertaken. Most of this work focuses on the analysis of several analog circuits, including their functionality, using different design methodologies. A "conventional" design methodology, based on the modeling where a current equation is obtained considering that the transistor is in the saturation region, and a design methodology based on the gm/ID characteristic, that allows a unified synthesis methodology in a11 regions of operation of the transistor. The analog circuits to be analyzed and designed in this work are basic building blocks (amplifiers, comparators and analog filters) that find vast applications today, including an application of interest - Sigma-Delta Modulators. The design methodology based on the g,,lI~ characteristic, and the electrical device parameters related to them, are exercised in this work. In order to demonstrate this analysis, electrical simulations (schematic and extracted layout) of performance will be obtained for each block.

Diferente do projeto de sistemas digitais, no qual as técnicas de projeto e ferramentas CAD vêm apresentando uma crescente evolução acompanhada da redução de seus preços, o projeto de sistemas analógicos CMOS ainda apresenta uma forte correlação com a experiência do projetista. Dentro deste contexto, importantes fatores como caracterização de tecnologia, modelamento de dispositivos e metodologia de projeto devem ser considerados. Este trabalho apresenta um estudo destes importantes fatores necessários para se realizar o projeto de um sistema analógico com menor custo, bom desempenho e reduzido tempo de projeto. Primeiramente, é necessária uma extensa caracterização da tecnologia CMOS a ser usada, onde os parâmetros que descrevem as caracteristicas elétricas dos dispositivos são obtidos. A partir desta caracterização e das especificações requeridas para o circuito, é feita uma modelagem e sintese a fim de se obter as dimensões dos transistores. Ferramentas para a análise do desempenho elétrico são utilizadas a seguir, antes de se realizar a descrição geométrica (layout) do circuito. Com o layout pronto, uma nova simulação elétrica é feita incluindo os efeitos geométricos, incluindo-se os parasitas R, C e L extraídos do layout. Se os resultados forem satisfatórios, o circuito está pronto para fabricação; havendo degradação do desempenho esperado, uma nova iteração de projeto é realizada. Mais especificamente, este trabalho ilustra o processo de análise de vários circuitos analógicos, assim como as caracteristicas de cada circuito em questão, empregando diferentes metodologias de projeto. Uma metodologia de projeto convencional, baseada em modelos onde se obtém uma equação explícita para a corrente válida na região de operação de saturação do transistor, e uma metodologia de projeto baseada na caracteristica g,/ID do transistor, que apresenta uma sintese unificada, considerando todas as regiões de operação do transistor MOS. Os circuitos a serem analisados e projetados neste trabalho são blocos considerados básicos para construção da maioria dos sistemas analógicos usados atualmente, como, por exemplo, Moduladores Sigma-Delta. Tais blocos são amplificadores, comparadores e filtros analógicos. A metodologia de projeto, baseada em parâmetros do modelo elétrico, é apresentada, enfatizando a caracteristica ~,/ID do transistor. Simulações elétricas serão realizadas (esquemático e layout extraído) para cada bloco, validando-se o projeto para as especificações requeridas. / Design techniques and CAD tools for digital systems are advancing rapidly at decreasing cost, while CMOS analog circuit design is related mostly with the individual experience and background of the designer. Therefore, the design of an analog circuit depends on several factors such as a reliable design methodology, good modeling and circuit fabrication technology characterization. This work presents a study of these factors that allow an analog system to be designed with high quality and performance at low cost, in a reasonable design time. First, an extensive characterization of the technology must be developed, where a11 the parameters that describe the electrical properties of the device are obtained. When this task is complete, an extensive analysis and modeling is made, transforming specifications into circuits with the transistor dimensions calculated. This leads to another important task - using electrical simulation to predict the performance of the circuit. Once the performance goals are satisfied, the designer is faced with the task of geometrical description (layout) of the circuit. Once the layout is finished, it is necessary to include the geometrical effects in a post-extraction simulation. If the results are satisfactory, the circuit is ready for fabrication. In case the specifications are not met, new design iteration must be undertaken. Most of this work focuses on the analysis of several analog circuits, including their functionality, using different design methodologies. A "conventional" design methodology, based on the modeling where a current equation is obtained considering that the transistor is in the saturation region, and a design methodology based on the gm/ID characteristic, that allows a unified synthesis methodology in a11 regions of operation of the transistor. The analog circuits to be analyzed and designed in this work are basic building blocks (amplifiers, comparators and analog filters) that find vast applications today, including an application of interest - Sigma-Delta Modulators. The design methodology based on the g,,lI~ characteristic, and the electrical device parameters related to them, are exercised in this work. In order to demonstrate this analysis, electrical simulations (schematic and extracted layout) of performance will be obtained for each block.

Diferente do projeto de sistemas digitais, no qual as técnicas de projeto e ferramentas CAD vêm apresentando uma crescente evolução acompanhada da redução de seus preços, o projeto de sistemas analógicos CMOS ainda apresenta uma forte correlação com a experiência do projetista. Dentro deste contexto, importantes fatores como caracterização de tecnologia, modelamento de dispositivos e metodologia de projeto devem ser considerados. Este trabalho apresenta um estudo destes importantes fatores necessários para se realizar o projeto de um sistema analógico com menor custo, bom desempenho e reduzido tempo de projeto. Primeiramente, é necessária uma extensa caracterização da tecnologia CMOS a ser usada, onde os parâmetros que descrevem as caracteristicas elétricas dos dispositivos são obtidos. A partir desta caracterização e das especificações requeridas para o circuito, é feita uma modelagem e sintese a fim de se obter as dimensões dos transistores. Ferramentas para a análise do desempenho elétrico são utilizadas a seguir, antes de se realizar a descrição geométrica (layout) do circuito. Com o layout pronto, uma nova simulação elétrica é feita incluindo os efeitos geométricos, incluindo-se os parasitas R, C e L extraídos do layout. Se os resultados forem satisfatórios, o circuito está pronto para fabricação; havendo degradação do desempenho esperado, uma nova iteração de projeto é realizada. Mais especificamente, este trabalho ilustra o processo de análise de vários circuitos analógicos, assim como as caracteristicas de cada circuito em questão, empregando diferentes metodologias de projeto. Uma metodologia de projeto convencional, baseada em modelos onde se obtém uma equação explícita para a corrente válida na região de operação de saturação do transistor, e uma metodologia de projeto baseada na caracteristica g,/ID do transistor, que apresenta uma sintese unificada, considerando todas as regiões de operação do transistor MOS. Os circuitos a serem analisados e projetados neste trabalho são blocos considerados básicos para construção da maioria dos sistemas analógicos usados atualmente, como, por exemplo, Moduladores Sigma-Delta. Tais blocos são amplificadores, comparadores e filtros analógicos. A metodologia de projeto, baseada em parâmetros do modelo elétrico, é apresentada, enfatizando a caracteristica ~,/ID do transistor. Simulações elétricas serão realizadas (esquemático e layout extraído) para cada bloco, validando-se o projeto para as especificações requeridas. / Design techniques and CAD tools for digital systems are advancing rapidly at decreasing cost, while CMOS analog circuit design is related mostly with the individual experience and background of the designer. Therefore, the design of an analog circuit depends on several factors such as a reliable design methodology, good modeling and circuit fabrication technology characterization. This work presents a study of these factors that allow an analog system to be designed with high quality and performance at low cost, in a reasonable design time. First, an extensive characterization of the technology must be developed, where a11 the parameters that describe the electrical properties of the device are obtained. When this task is complete, an extensive analysis and modeling is made, transforming specifications into circuits with the transistor dimensions calculated. This leads to another important task - using electrical simulation to predict the performance of the circuit. Once the performance goals are satisfied, the designer is faced with the task of geometrical description (layout) of the circuit. Once the layout is finished, it is necessary to include the geometrical effects in a post-extraction simulation. If the results are satisfactory, the circuit is ready for fabrication. In case the specifications are not met, new design iteration must be undertaken. Most of this work focuses on the analysis of several analog circuits, including their functionality, using different design methodologies. A "conventional" design methodology, based on the modeling where a current equation is obtained considering that the transistor is in the saturation region, and a design methodology based on the gm/ID characteristic, that allows a unified synthesis methodology in a11 regions of operation of the transistor. The analog circuits to be analyzed and designed in this work are basic building blocks (amplifiers, comparators and analog filters) that find vast applications today, including an application of interest - Sigma-Delta Modulators. The design methodology based on the g,,lI~ characteristic, and the electrical device parameters related to them, are exercised in this work. In order to demonstrate this analysis, electrical simulations (schematic and extracted layout) of performance will be obtained for each block.

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