Dynamic Voltage Scaling (DVS) and Adaptive body bias (ABB) techniques respectively try to reduce the dynamic and static power components of an integrated circuit. Ideally, the two techniques can be combined to find the optimal operating voltages (VDD and VBB) to minimize power consumption. A combination of the DVS and ABB may warrant the circuit to operate at voltages (supply and body bias) different from the values specified by the two methods working independently. Also, this VDD and VBB values for minimal power consumption varies with the workload of the circuit. The workload can be used as an index to select the optimal VDD/VBB values to minimize the total power consumption. This paper examines the optimal voltages for minimal power operation for typical data path circuits like adders and multiply-accumulate (MAC) units across various process, voltage, and temperature conditions and under different workloads. In addition, a workload based look up table to minimize the power consumption is also proposed. Simulation results for an adder and a multiply-accumulate circuit block indicate a power saving of 12-30% over standard DVS scheme.
| Identifer | oai:union.ndltd.org:IISc/oai:etd.ncsi.iisc.ernet.in:2005/1030 |
| Date | 08 1900 |
| Creators | Sreejith, K |
| Contributors | Amrutur, Bharadwaj |
| Source Sets | India Institute of Science |
| Language | en_US |
| Detected Language | English |
| Type | Thesis |
| Relation | G23462 |
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