Trend towards downsizing the product size and at the same time to bring more functionality in electronic products, demands electrically interconnecting several miniaturized electronic components with high counts of I\Os (Input/Out put) on smaller and smaller size printed wiring boards [PWB]. These miniature components occupy lower foot print area but require higher routing interconnection densities. However, the conventional multilayer board technologies exhibit limitations when there is need to connect very high I\O components such as ball grid arrays, which require blind and buried interconnections within the multilayer mono-block. This limitation has given raise to newer methods of multi layer construction.
Build–up multilayer PWB is now the technology of choice for enhanced routing capability including blind and buried interlayer connections. Build up methods are based on making very small vias within dielectric layers followed by metalisation. Typically blind and buried vias are very small, and hence called “micro vias” connecting the layers selectively within the multilayer mono-block. Buried vias make the interconnection between the consecutive layers, and blind vias connect the surface layers to any one of the interior layers in the build up multilayer board. If the blind vias are filled with a dielectric, the entire top and bottom surface area becomes available for high -density component mounting.
The crux in build up board technologies is the method of creating micro-holes; a micro hole is a hole, which is less than 150 micro meter in diameter. Efforts are made to replace existing metalising techniques with “paste filling” methodologies, which would result in “SOLID CONDUCTING VIAS” CALLED AS “MICRO -INTERCONNECTS” The work reported in this thesis aims at demonstrating one such innovative ‘solid conducting via’ formation without using any of the known micro-hole formation techniques. Based on the results obtained some useful conclusions have been drawn which will perhaps go a long way in the name of “PRINTED PILLAR TECHNOLOGY” a novel methodology for building multilayer suitable for very high I\O components such as “ball grid arrays.”
| Identifer | oai:union.ndltd.org:IISc/oai:etd.ncsi.iisc.ernet.in:2005/846 |
| Date | 01 1900 |
| Creators | Bhat, Shriram N |
| Contributors | Rao, G Anand |
| Source Sets | India Institute of Science |
| Language | en_US |
| Detected Language | English |
| Type | Thesis |
| Relation | G22215 |
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