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Circuit Design of LDPC Decoder for IEEE 802.16e Standard

In this thesis, a multi-rate LDPC (Low-Density Parity-Check code) decoder circuit is proposed for IEEE 802.16e standard. In the proposed circuit, we modify the overlapping structure for different code rate of the LDPC decoder to enhance the hardware utilization ratio and provide flexible parametric design. LDPC decoding is completed by the recursive operations between variable nodes and check nodes. We use Beneš network to implement the wire-routing of the operations between variable nodes and check nodes. However, the decoders with different code rates may result in different Beneš networks and increase the hardware complexity. We propose a modified overlapping structure to reduce the complexity of parallelized Beneš network and to increase the hardware utilization ratio.

Identiferoai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0830110-020034
Date30 August 2010
CreatorsChen, Cheng-Ho
Contributorsnone, none, none
PublisherNSYSU
Source SetsNSYSU Electronic Thesis and Dissertation Archive
LanguageCholon
Detected LanguageEnglish
Typetext
Formatapplication/pdf
Sourcehttp://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0830110-020034
Rightsnot_available, Copyright information available at source archive

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