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Implementation and Design of a Bit-Error Generator and Logger for Multi-Gigabit Serial Links

<p>Test Tools are very important in the design of a system. They generally simulate a working environment, only at a higher</p><p>speed, or with less frequently occurring test cases. In the verification of protocols based on the Fibre Channel physical layer,</p><p>this becomes a necessity, as errors can be non-existent or very unusual in normal operating environments. Most systems need</p><p>to be able to handle these unexpected events nonetheless. Therefore, there is a need for a method of introducing these errors</p><p>in a controlled way.</p><p>A bit error generation and logging tool for two proprietary protocols based on the Fibre Channel physical layer has been</p><p>developed. The hardware platform consists mainly of a Virtex II Pro FPGA with accompanying I/O support. Control of the</p><p>hardware is handled by a graphical user interface residing on a PC. Communication between the hardware and the PC is</p><p>handled with a UART. The final implementation can handle four parallel one way links, or two full duplex links,</p><p>independently. This report describes the implementation and the necessary theoretical background for this.</p>

Identiferoai:union.ndltd.org:UPSALLA/oai:DiVA.org:liu-7268
Date January 2006
CreatorsBotella, Pedro
PublisherLinköping University, Department of Electrical Engineering, Institutionen för systemteknik
Source SetsDiVA Archive at Upsalla University
LanguageEnglish
Detected LanguageEnglish
TypeStudent thesis, text

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