Real-time aspects are becoming more important in
standard desktop PC environments and x86 based
processors are being utilized in embedded systems
more often.
While these processors were not created for use
in hard real time systems, they are fast and
inexpensive and can be used if it is possible
to determine the worst case execution time.
Information on CPU caches (L1, L2) and
branch prediction architecture is necessary
to simulate best and worst cases in execution
timing, but is often not detailed
enough and sometimes not published at all.
This document describes how the underlying
hardware can be analysed to obtain
this information.
| Identifer | oai:union.ndltd.org:DRESDEN/oai:qucosa.de:swb:ch1-200501401 |
| Date | 19 October 2005 |
| Creators | John, Tobias |
| Contributors | TU Chemnitz, Fakultät für Informatik, TU Chemnitz, Fakultät für Elektrotechnik und Informationstechnik, Dr. Robert Baumgartl, Prof. Peter Protzel, Dr. Robert Baumgartl |
| Publisher | Universitätsbibliothek Chemnitz |
| Source Sets | Hochschulschriftenserver (HSSS) der SLUB Dresden |
| Language | English |
| Detected Language | English |
| Type | doc-type:masterThesis |
| Format | text/html, application/pdf, application/x-gzip, text/plain, application/zip |
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