With increasing demands in terms of timing, area and power, today’s ASIC (Application Specific Integrated Circuit) designers are faced with new problems as technology emerges. Ericsson has started to work in 65 nm and realized that the methods used in previous, larger technologies, does not offer good enough correlation between synthesis and the results after physical placement. This leads to several expensive and time consuming iterations back and forth between Ericsson and the ASIC vendor. In order to narrow the gap between Ericsson and the ASIC vendor, and hence increase correlation, physical planning has been identified as a possible solution. Cadence First Encounter, part of the Cadence Encounter digital IC design platform, is an advanced tool for silicon virtual prototyping. The tool basically brings back-end placement knowledge to front-end ASIC designers. This master’s thesis main goal is to evaluate Cadence First Encounter and investigate how it could be integrated with Ericsson’s design flow. The tool has been tested on previous designs with known issues and the results are positive. By using the prototype work flow in First Encounter that is described in this report, it is possible to identify and correct issues with the netlists in time, which will help shortening the lead time in projects and hence also the time to market.
| Identifer | oai:union.ndltd.org:UPSALLA1/oai:DiVA.org:liu-8641 |
| Date | January 2007 |
| Creators | Roos, Håkan |
| Publisher | Linköpings universitet, Institutionen för systemteknik, Institutionen för systemteknik |
| Source Sets | DiVA Archive at Upsalla University |
| Language | English |
| Detected Language | English |
| Type | Student thesis, info:eu-repo/semantics/bachelorThesis, text |
| Format | application/pdf |
| Rights | info:eu-repo/semantics/openAccess |
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