Clock mesh is widely used in microprocessor designs for achieving low clock
skew and high process variation tolerance. Clock mesh optimization is a very diffcult
problem to solve because it has a highly connected structure and requires accurate
delay models which are computationally expensive.
Existing methods on clock network optimization are either restricted to clock
trees, which are easy to be separated into smaller problems, or naive heuristics based
on crude delay models.
A clock mesh sizing algorithm, which is aimed to minimize total mesh wire area
with consideration of clock skew constraints, has been proposed in this research work.
This algorithm is a systematic solution search through rigorous Sequential Quadratic
Programming (SQP). The SQP is guided by an efficient adjoint sensitivity analysis
which has near-SPICE(Simulation Program for Integrated Circuits Emphasis)-level
accuracy and faster-than-SPICE speed.
Experimental results on various benchmark circuits indicate that this algorithm
leads to substantial wire area reduction while maintaining low clock skew in the clock
mesh. The reduction in mesh area achieved is about 33%.
| Identifer | oai:union.ndltd.org:tamu.edu/oai:repository.tamu.edu:1969.1/ETD-TAMU-2010-05-7753 |
| Date | 2010 May 1900 |
| Creators | Mekala, Venkata |
| Contributors | Hu, Jiang |
| Source Sets | Texas A and M University |
| Language | English |
| Detected Language | English |
| Type | Book, Thesis, Electronic Thesis, text |
| Format | application/pdf |
Page generated in 0.002 seconds