The system clock has been omnipresent in most mainstream chip designs. While simplifying many design problems the clock has caused the problems of clock skew, high power consumption, electromagnetic interference, and worst-case performance. In recent years, as the timing constraints of synchronous designs have been squeezed ever tighter, the efficiencies of asynchronous designs have become more attractive. By removing the clock, these issues can be mitigated. How- ever, asynchronous designs are generally more complex and difficult to debug. In this paper I discuss the advantages of asynchronous processors and the specifics of some asynchronous designs, outline the roadblocks to asynchronous processor design, and propose a series of asynchronous designs to be used by students in tandem with traditional synchronous designs when taking an undergraduate computer architecture course.
| Identifer | oai:union.ndltd.org:CALPOLY/oai:digitalcommons.calpoly.edu:theses-1399 |
| Date | 01 August 2010 |
| Creators | Webb, Robert L |
| Publisher | DigitalCommons@CalPoly |
| Source Sets | California Polytechnic State University |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | Master's Theses |
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