Decision feedback equalizer (DFE) is an effective method to remove inter-symbol
interference (ISI) from a disk-drive read channel. Analog IC implementations of DFE
potentially offers higher speed, smaller die area, and lower power consumption when
compared to their digital counterparts.
Most of the available DFE equalizers were realized by using digital FIR filters
preceded by a flash A/D converter. Both the FIR filter and flash A/D converter are the
major contributers to the power dissipation. However, this project focuses on the analog
IC implementations of the DFE to achieve high speed and low power consumption. In
other words, this project gets intensively involved in the design of a large-input highly-linear
voltage-to-current converter, the design of a high-speed low-power 6-bit
comparator, and the design of a high-speed low-power 6-bit current-steering D/A
converter.
The design and layout for the proposed analog equalizer are carried out in a 1.2
pm n-well CMOS process. HSPICE simulations show that an analog DFE with 100 MHz
clock frequency and 6-bit accuracy can be easily achieved. The power consumption for
all the analog circuits is only about 24mW operating under a single 5V power supply. / Graduation date: 1997
| Identifer | oai:union.ndltd.org:ORGSU/oai:ir.library.oregonstate.edu:1957/34496 |
| Date | 08 July 1996 |
| Creators | Su, Wenjun |
| Contributors | Allstot, David |
| Source Sets | Oregon State University |
| Language | en_US |
| Detected Language | English |
| Type | Thesis/Dissertation |
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