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Mapování vyhledávacích tabulek z jazyka P4 do technologie FPGA / Mapping of Match Tables from P4 Language to FPGA Technology

This thesis deals with design and implementation of mapping of match action tables from P4 language to FPGA technology. Goal of the thesis was to describe key principles, which need to be understood in order to design such a mapping and function of algorithms needed, apply these principles by implementing them and analyze the speed and memory requirements of such an implementation. Outcome provides configurable hardware unit capable of classifying packets and connection between the unit and match action tables from P4 language. The implementation is based on DCFL algorithm and requires less memory compared to HiCuts and HyperCuts algorithms while being comparably fast at worst-case scenarios.

Identiferoai:union.ndltd.org:nusl.cz/oai:invenio.nusl.cz:255356
Date January 2016
CreatorsKekely, Michal
ContributorsMatoušek, Jiří, Kořenek, Jan
PublisherVysoké učení technické v Brně. Fakulta informačních technologií
Source SetsCzech ETDs
LanguageCzech
Detected LanguageEnglish
Typeinfo:eu-repo/semantics/masterThesis
Rightsinfo:eu-repo/semantics/restrictedAccess

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