Return to search

Programmable DLL-based Frequency Multiplier and A ROM-less Direct Digital Frequency Synthesizer

This thesis includes two topics. The first topic is a programmable DLL-based frequency multiplier, which can be a local oscillator in RF applications. The second one is a ROM-less direct digital frequency synthesizer to serve as a good reference clock or to be used in digital modulation and demodulation.
A CMOS local oscillator using a programmable DLL-based frequency multiplier is presented. In this work, low-Q on-chip inductors are not needed. The clock of the output frequency is digitally controllable, which is ranged from 7´ to 10´ of an input reference clock. The design is carried out by TSMC 1P5M 0.25 mm CMOS process at 2.5 V power supply. The output frequency range of the physical chips measurement is about 1.0 GHz ~ 1.5 GHz. Maximum power dissipation is 58.2 mW at 1.5 GHz output.
A ROM-less direct digital frequency synthesizer (DDFS) employing trigonometric quadruple angle formula is presented. In a system-level simulation, the spurious tones performance is suppressed to be lower than -130 dBc. The resolution is up to 13 bits. The maximum error is also analyzed mathematically to meet the simulation results.

Identiferoai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0625102-111310
Date25 June 2002
CreatorsShe, Hsien-Chih
ContributorsChua-Chin Wang, Sying-Jyan Wang, Chi-Feng Wu, Ing-Jer Huang
PublisherNSYSU
Source SetsNSYSU Electronic Thesis and Dissertation Archive
LanguageCholon
Detected LanguageEnglish
Typetext
Formatapplication/pdf
Sourcehttp://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0625102-111310
Rightsnot_available, Copyright information available at source archive

Page generated in 0.0013 seconds