AbstractDifferent approaches for implementing a complex multiplier in pipelined FFT are considered andimplemented to find an efficient one in this project. The implemented design is synthesized on Cyclone IIand Stratix III to know the performance. The design is implemented with a focus of reducing the resourcesused. Some approaches resulted in the reduced number of DSP blocks and others resulted in reducednumber of LUTs. Analysis of Synthesis results is performed for different widths (bit lengths) of complexmultiplier approaches.
| Identifer | oai:union.ndltd.org:UPSALLA1/oai:DiVA.org:liu-16547 |
| Date | January 2009 |
| Creators | Thangella, Praneeth Kumar, Gundla, Aravind Reddy |
| Publisher | Linköpings universitet, Institutionen för systemteknik, Linköpings universitet, Institutionen för systemteknik |
| Source Sets | DiVA Archive at Upsalla University |
| Language | English |
| Detected Language | English |
| Type | Student thesis, info:eu-repo/semantics/masterThesis, text |
| Format | application/pdf |
| Rights | info:eu-repo/semantics/openAccess |
Page generated in 0.0022 seconds