A circuit design of baseband transceiver for direct sequence ultra-wide band system is presented in this thesis. A low complexity Viterbi decoder is also proposed. This Viterbi decoder circuit is based on compare-select-add unit and trace-forward architecture. The decision bit operator is reduced to one adder and this can lower down the hardware complexity. Further, two trace-forward operators are used in the survivor management unit. Only two single port SRAM¡¦s with a length of T are applied for reducing the area of memory.
The chip is implemented by TSMC standard 0.18-£gm 1P6M CMOS process with core area 1.061 ¡Ñ 1.069 mm2. The post-layout simulation with 1.8V supply at 25 shows that the proposed direct sequence ultra-wide band system of baseband transceiver chip can work above 141 MHz with 86.41 mW power dissipation.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0626109-132754 |
| Date | 26 June 2009 |
| Creators | Huang, Chun-Yuan |
| Contributors | Szu-Lin Su, Ching-piao Hung, Ju-ya Chen, Cin-de Wan |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0626109-132754 |
| Rights | not_available, Copyright information available at source archive |
Page generated in 0.0019 seconds