In this thesis, a 14-bit low-power Analog-to-Digital Converter (ADC) is designed for sensor applications. Following on previous work, the ADC is designed to be frequency scalable by 1000 times from 1.67S/s to 1.67kS/s. To reduce power, class AB opamps are used. The design was fabricated in 0.18um CMOS and occupies an area of 0.35mm2. Operating at full-rate as a Delta-Sigma modulator, the ADC achieves 91.8dB peak SNDR while consuming 83uW. In incremental mode, the ADC powers off periodically to achieve frequency scalability, maintaining 84.7dB to 89dB peak SNDR while operating from 1.67S/s to 1.67kS/s.
| Identifer | oai:union.ndltd.org:LACETR/oai:collectionscanada.gc.ca:OTU.1807/18802 |
| Date | 15 February 2010 |
| Creators | Liang, Joshua |
| Contributors | Johns, David A. |
| Source Sets | Library and Archives Canada ETDs Repository / Centre d'archives des thèses électroniques de Bibliothèque et Archives Canada |
| Language | en_ca |
| Detected Language | English |
| Type | Thesis |
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